NAND Flash Memory Bit Line Voltage Control for Program Speed
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Solution Overview
Problem
As NAND flash memory cells are miniaturized, variations in impurity amounts and cell shape lead to degraded program performance and wider threshold voltage distribution, requiring smaller step-up voltages to improve threshold distribution, but this results in slower program speed due to increased program loops.
Innovation Solution
A nonvolatile semiconductor memory device that controls bit line voltages during programming, charging bit lines connected to memory cells to specific voltages based on their program states, allowing for a higher initial program voltage while preventing over-programming, thereby reducing the number of program loops and increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a small step-up voltage is used for program voltage, then threshold voltage distribution is improved and suppressed, but program speed is lowered due to larger number of program loops required
Solution Approach 1:
The patent segments the programming process into multiple stages with different bit line voltage levels. Memory cells are divided into groups based on their programming status, with different voltage levels applied to different groups. This allows simultaneous optimization of threshold distribution (through controlled voltage steps) and programming speed (through parallel processing of multiple cell groups), resolving the contradiction between precision and productivity.
Solution Approach 2:
The patent applies preliminary actions by pre-charging bit lines to specific voltage levels before programming operations. By preparing bit lines in advance with appropriate voltage levels, the system can quickly transition between different programming stages without waiting for voltage buildup, thereby maintaining tight threshold distribution while reducing overall programming time and improving speed.
2Quantity of substance
If memory cells are further miniaturized, then storage density is improved, but program performance is degraded due to variation in impurity amounts and cell shape
Solution Approach 1:
The patent applies local quality by tailoring the programming voltage levels and timing to the specific characteristics of miniaturized memory cells. Different regions or groups of cells receive customized voltage profiles based on their individual programming status and physical characteristics. This localized approach compensates for variations in impurity amounts and cell shape, maintaining reliable program performance despite further miniaturization for higher storage density.
3Productivity
If a higher initial program voltage is applied, then program speed is increased by reducing program loops, but over-programming occurs degrading threshold voltage distribution
Solution Approach 1:
The patent implements dynamics by making bit line voltage levels changeable and adaptive during the programming process. Instead of applying a fixed high voltage that causes over-programming, the system dynamically adjusts voltage levels based on real-time feedback from verify operations. This allows the system to maintain high initial voltages for speed while preventing over-programming through adaptive control, thus preserving threshold voltage distribution precision.
Solution Approach 2:
The patent incorporates feedback mechanisms where verify operations monitor the programming status of memory cells, and this information feeds back to control subsequent programming voltage applications. By using feedback to detect when cells have reached their target threshold voltage, the system can stop programming individual cell groups at the optimal moment, preventing over-programming while maintaining overall fast programming speed through reduced loop iterations.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed.