Non-Volatile Memory Page Buffer Timing Control
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Solution Overview
Problem
In NAND-type EEPROMs, the varying write speeds among memory cells lead to incorrect data detection during read operations due to threshold voltage discrepancies, causing issues with data accuracy and leakage current, especially when a large number of memory cells are programmed to '1', which complicates the timing of data input and detection in the page buffer.
Innovation Solution
A non-volatile memory device with a control circuit that adjusts the data input time and detection time in the page buffer based on the voltage level of the common source line, utilizing a differential amplifier, timer, and core controller to manage the connection and disconnection of bit lines and transistors, ensuring accurate data transfer and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written using tunnel current in NAND-type EEPROM, then write operation is performed, but data write speed varies among memory cells causing threshold voltage discrepancies
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation to detect the threshold voltage state of memory cells. Based on this preliminary detection, the system determines whether to proceed with the write operation or skip it, thereby preventing threshold voltage discrepancies and ensuring data accuracy.
2Quantity of substance
If memory cells are programmed to '1' in large numbers, then storage capacity is utilized, but leakage current increases and data detection becomes inaccurate
Solution Approach 1:
The patent implements feedback by using the result of the pre-read operation to control subsequent write operations. The read operation provides feedback information about the threshold voltage state, which feeds back to the control logic to determine whether to perform the write operation, thereby preventing leakage current issues and ensuring accurate data detection.
3Device complexity
If fixed timing is used for data input and detection in page buffer, then operation is simplified, but incorrect data is written to latch due to voltage level variations
Solution Approach 1:
The patent applies dynamics by making the timing of data input and detection adaptive rather than fixed. The timing is dynamically adjusted based on the voltage level of the common source line, which varies depending on the number of programmed memory cells. This dynamic timing adjustment ensures accurate data detection while preventing incorrect data from being written to the latch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents incorrect data from being written to the latch, reduces total leakage current, and optimizes the read operation by adjusting the timing of data input and detection according to the number of programmed memory cells, thereby enhancing data accuracy and operational efficiency.
Implementation Method 1
a differential amplifier configured to compare a potential of the common source line with a predetermined reference voltage and to output a detection signal
Implementation Method 2
a timer configured to measure time in response to the detection signal received from the differential amplifier and to output a time signal after a certain time
Implementation Method 3
a tunnel oxide layer formed in a channel region between the source region and the drain region... electrons are injected from the channel to a floating gate
Data Source
AI summary
A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell.