Sense Amplifier Bit Line Precharge and Charge Transfer
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Solution Overview
Problem
Sense amplifiers in semiconductor memory devices face challenges in accurately sensing small cell currents, leading to reduced sense margin and slower sensing times, especially in NAND-type flash memories, due to incomplete charging and discharging of bit lines which affects the difference in current and potential between on-cell and off-cells.
Innovation Solution
A sense amplifier configuration with a first transistor for precharging the bit line via two sense nodes, a second transistor for charge transfer between these nodes, and a third transistor for continuous current supply, allowing selective charge transfer and improved voltage control to enhance sensing accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the sense amplifier uses the voltage sense type to precharge and discharge the bit line, then power consumption is reduced, but sensing speed decreases and sense margin is reduced due to incomplete charging/discharging
Solution Approach 1:
The patent divides the sensing operation into two distinct phases: a precharge phase that charges the bit line to a predetermined voltage level, and a sensing phase that detects voltage changes without full discharge. This segmentation allows the system to benefit from reduced power consumption during precharge while maintaining fast sensing capability during the detection phase, resolving the contradiction between energy efficiency and sensing speed.
Solution Approach 2:
The patent performs preliminary charging of the bit line to a predetermined voltage level before the actual sensing operation. This preliminary action ensures that the bit line is ready for rapid detection without requiring full discharge during sensing, thereby maintaining both low power consumption and fast sensing speed by preparing the system in advance.
2Measurement precision
If the sense amplifier uses the voltage sense type with large amplitude bit line voltage changes, then sensing capability is improved, but noise interference between adjacent bit lines increases
Solution Approach 1:
The patent applies different voltage amplitude characteristics to different operational phases: large voltage swings are used only during the precharge phase to ensure complete charging, while the sensing phase uses controlled, smaller voltage changes. This local differentiation of voltage characteristics maintains sensing capability while minimizing noise interference between adjacent bit lines during the critical sensing operation.
Solution Approach 2:
The patent employs periodic switching between precharge and sensing phases, where the bit line voltage is deliberately changed to a predetermined level during precharge and then maintained at controlled levels during sensing. This periodic action with distinct voltage characteristics for each phase enables accurate sensing while reducing continuous large-amplitude voltage changes that cause noise interference.
3Object-affected harmful factors
If the sense amplifier uses the current sense type with clamp transistor to suppress bit line voltage amplitude, then noise between bit lines is reduced, but sensing margin is reduced due to incomplete charge transfer
Solution Approach 1:
The patent performs preliminary charging of the bit line to a predetermined voltage level before sensing, ensuring that sufficient charge is available for accurate detection. This preliminary action compensates for any charge loss during sensing, maintaining sensing margin even when the clamp transistor suppresses large voltage swings and reduces noise between adjacent bit lines.
Solution Approach 2:
The patent introduces a predetermined voltage level as an intermediary reference point for the bit line during precharge. This intermediary voltage level serves as a stable reference that ensures complete charging without requiring large voltage swings during sensing, thereby maintaining sensing margin while the clamp transistor suppresses noise between bit lines through controlled voltage suppression.
4Productivity
If all bit lines are sensed in parallel using ABL type with continuous current supply, then sensing speed is improved, but sense margin is reduced due to charge discharge to bit line
Solution Approach 1:
The patent performs preliminary charging of each bit line to a predetermined voltage level before parallel sensing operations. This preliminary action ensures that each bit line has sufficient charge reservoir to maintain stable voltage during sensing, preserving sensing margin even when multiple bit lines are sensed simultaneously with continuous current supply enabled for fast parallel operation.
Solution Approach 2:
The patent changes the voltage parameter of the bit line to a predetermined level during precharge, creating a stable reference state that maintains sensing margin during parallel operations. By establishing this predetermined voltage level before sensing, the system can perform fast parallel sensing with continuous current supply while maintaining adequate sense margin through the stabilized voltage parameter.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves sense margin by maintaining steady bit line voltage, enabling faster sensing and reducing noise between adjacent bit lines, even when all bit lines are sensed simultaneously.
Implementation Method 1
a first transistor for precharge to supply current in the bit line via a first and a second sense node
Implementation Method 2
a second transistor for charge transfer interposed between the first and second sense nodes
Implementation Method 3
a third transistor for continuous current supply to supply current in the bit line not via the first and second sense nodes
Data Source
AI summary
A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.