Sense Amplifier Offset Compensation in Flash Memory

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Solution Overview

Problem

Conventional semiconductor devices with sense amplifiers face challenges in read speed due to offset compensation circuits that require frequent capacitor charging, leading to complexity and reduced read speed.

Innovation Solution

A semiconductor device design where sense amplifiers are activated after precharging both nodes to the same voltage, allowing for voltage reduction based on the output signal, thereby simplifying the configuration and accelerating read speed without the need for multiple capacitor stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two capacitors are charged every read operation to compensate for offset voltage, then offset compensation is achieved, but read speed is decelerated

Engineering Contradiction:
Improveoffset compensationVSAvoidread speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by precharging both nodes to the same voltage before activating the sense amplifier. This preliminary equalization of node voltages eliminates the need for repeated capacitor charging during read operations, as the offset compensation is achieved through the initial precharging phase rather than continuous capacitor operations during each read cycle

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the capacitance value of the capacitor is changed to a plurality of stages for each data bus, then read data signals can be stored, but the configuration becomes complicated

Engineering Contradiction:
Improveread data signal storageVSAvoidcapacitor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the offset compensation function from the read data storage function. By using a single capacitor for offset compensation while maintaining separate precharge and sense amplifier circuits for data storage, the invention separates these functions that were previously combined in multi-stage capacitor configurations, thereby simplifying the overall circuit structure while preserving read data signal storage capability

Inventive Principle:
Principle #2Taking out (Extraction)

3Speed

If a sense amplifier is activated after node voltage equalization, then read speed is accelerated, but offset voltage may affect accuracy

Engineering Contradiction:
Improveread speedVSAvoidvoltage measurement accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent applies preliminary anti-action by precharging both nodes to the same voltage before sense amplifier activation. This preliminary action counteracts the offset voltage effect by ensuring both nodes start at identical voltage levels, thereby eliminating the need for separate offset compensation operations while maintaining measurement accuracy through the initial equalization

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS9053806B2Semiconductor device
Publication Date: 2015.06.09 RENESAS ELECTRONICS CORP
  • US9053806B2 patent drawing
  • US9053806B2 patent drawing
  • US9053806B2 patent drawing

AI summary

In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant current source for offset compensation is connected to the first or second node. Accordingly, the offset voltage of the sense amplifier can be compensated for with a simple configuration.