Memory Device De-trap Operation for Stable Verify

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Solution Overview

Problem

Current nonvolatile semiconductor memory devices face challenges in achieving high-speed and reliable data write operations due to electron trapping in the gate insulation film during program operations, which can lead to noise and instability during verify operations.

Innovation Solution

The memory device executes a de-trap operation while charging the bit line for program verify, ensuring stable electrons are targeted for verification, and employs specific voltage control strategies to suppress hot carrier generation and channel boost weakening.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If program operation is executed at high speed, then productivity is improved, but electron trapping in gate insulation film increases causing noise and instability during verify operations

Engineering Contradiction:
Improveprogram operation speedVSAvoidverify operation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by executing a de-trap operation before the verify operation to remove trapped electrons from the gate insulation film. This preliminary cleanup action ensures that subsequent verify operations target only stable electrons, preventing noise and instability while maintaining high-speed program operations

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If program voltage is applied to selected memory cell, then data is programmed, but hot carrier generation occurs causing electron trapping

Engineering Contradiction:
Improvedata programming accuracyVSAvoidhot carrier generation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful effect of hot carrier generation into a beneficial process by using the trapped electrons as a target for the de-trap operation. The de-trap operation specifically removes these hot carrier-induced trapped electrons, transforming the harmful noise into a controllable parameter that can be cleaned up before verification

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Measurement precision

If verify operation targets all electrons, then comprehensive verification is achieved, but noise from trapped electrons reduces measurement precision

Engineering Contradiction:
Improveelectron verification accuracyVSAvoidtrapped electron noise
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies the extraction principle by selectively removing trapped electrons from the gate insulation film through the de-trap operation. This extraction process separates harmful trapped electrons from stable electrons, allowing the verify operation to focus exclusively on stable electrons and achieve high measurement precision without noise interference

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high-speed and high-reliability data write operations by reducing noise and maintaining channel boost integrity, thereby improving data reliability and operational efficiency.

Implementation Method 1

electron trapping in the gate insulation film during program operations

Methodology Applied
Scientific EffectElectron trapping: Electron Paramagnetic Resonance

Implementation Method 2

suppress hot carrier generation

Methodology Applied
Scientific EffectHot carrier generation: Electron Avalanche

Implementation Method 3

while charging the bit line, a voltage of a control gate electrode

Methodology Applied
Scientific EffectElectric field effect: Electric Field

Data Source

PatentUS9627087B2Memory device
Publication Date: 2017.04.18 KIOXIA CORP
  • US9627087B2 patent drawing
  • US9627087B2 patent drawing
  • US9627087B2 patent drawing

AI summary

According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.