MLC NAND Flash Memory Page Buffer Common Line Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory array designs face inefficiencies due to a large periphery area, particularly in MLC NAND flash memory, which hinders increased memory density and performance, as they require extensive circuitry for page buffers and data detectors.
Innovation Solution
The proposed solution eliminates the need for data detectors by using a common line connected in parallel to each page buffer, with individual pass/fail circuits for each bit rank, allowing parallel operations and combining outputs through OR logic to determine successful programming of all cells within a byte, thereby reducing the periphery area and enhancing array efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional data detector circuitry is used in MLC NAND flash memory, then reliable pass/fail determination of memory cells is achieved, but the periphery area increases significantly
Solution Approach 1:
The patent extracts and eliminates the data detector circuitry from the memory architecture, replacing it with a simplified system using common lines connected to page buffers. This removal of unnecessary components directly reduces the periphery area while maintaining pass/fail determination functionality through alternative means (common line voltage sensing).
Solution Approach 2:
The common lines serve multiple functions: they act as bit lines for data transfer, sense lines for reading cell states, and verification lines for pass/fail determination. This multi-functionality eliminates the need for separate data detector circuitry, reducing periphery area while maintaining reliability.
2Ease of operation
If extensive circuitry for page buffers and data detectors is included, then complete data detection and verification capability is provided, but array efficiency decreases
Solution Approach 1:
By removing the data detector circuitry, the patent eliminates a major source of periphery area that reduces array efficiency. The extraction maintains essential data detection capability through the simplified common line interface while removing redundant functionality.
Solution Approach 2:
The patent merges the functions of data detection, verification, and pass/fail determination into the existing page buffer and common line infrastructure. This consolidation eliminates separate circuitry blocks, increasing array efficiency while preserving complete data detection capability.
3Measurement precision
If separate detection circuits are used for each byte, then precise byte-level verification is achieved, but device complexity increases
Solution Approach 1:
The common lines provide universal verification capability for all bytes simultaneously through parallel operation. Each page buffer independently monitors its associated byte on the common line, achieving byte-level precision without requiring separate dedicated detection circuits for each byte, thus reducing device complexity.
Data Source
AI summary
Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.