Flash Memory Low-Speed Read Mode Charge Pump Control Circuit
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Solution Overview
Problem
The existing flash-memory low-speed read mode consumes excessive current due to the charge pump operating in a waiting mode, leading to high power consumption.
Innovation Solution
A flash-memory low-speed read mode control circuit that switches between data read and charge pump electric-leakage modes, maintaining the output voltage above the low threshold voltage to prevent unnecessary charging, thereby reducing current consumption and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the charge pump operates in the waiting mode to maintain voltage above threshold, then the voltage stability is improved, but the current consumption increases significantly
Solution Approach 1:
The charge pump operates periodically rather than continuously. During active read operations, the charge pump is enabled to maintain voltage above the threshold. During waiting modes between address conversions, the charge pump is disabled to reduce current consumption. This periodic activation based on operational state transitions resolves the contradiction between maintaining voltage stability and reducing energy consumption.
Solution Approach 2:
The charge pump's operating state is dynamically adjusted based on the read mode. The system transitions between enabled and disabled states of the charge pump depending on whether an active read operation is occurring or if the system is in a waiting state. This dynamic control allows the system to optimize between voltage stability requirements and current consumption reduction.
2Reliability
If the charge pump operates continuously to maintain output voltage, then the voltage remains above threshold voltage, but the average current in low-speed read mode increases
Solution Approach 1:
The charge pump is activated only during active read operations and disabled during waiting periods. This periodic operation ensures voltage maintenance reliability when needed while improving overall system efficiency by eliminating unnecessary operation during idle waiting modes between address conversions.
3Use of energy by moving object
If the charge pump is disabled in waiting mode to reduce current, then the average current decreases, but the voltage may drop below threshold voltage
Solution Approach 1:
The charge pump's state is dynamically controlled based on the operational phase. During active read operations, the charge pump is enabled to maintain voltage stability. During waiting modes between address conversions, the charge pump is disabled to reduce current consumption. This dynamic state transition ensures voltage stability is maintained only when necessary, optimizing the balance between current consumption and voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces the average current and power consumption during the low-speed read mode by avoiding charge pump operation in the waiting mode, minimizing current draw and maintaining efficient data read processes.
Implementation Method 1
a charge pump, whose output terminal produces an output voltage when the charge pump is working
Implementation Method 2
an output terminal of the charge pump is connected to a first voltage division circuit, which includes a first resistor, a second resistor and a first switch connected in series
Implementation Method 3
the second terminal of the first resistor outputs a first component voltage of the output voltage, which first component voltage is connected to a positive input terminal of the comparator; a negative input terminal of the comparator is connected to a supply voltage
Implementation Method 4
the output terminal of the comparator is connected to a first input terminal of an NAND gate, with an output terminal of the NAND gate connected to the input terminal of the charge pump through a first buffer
Implementation Method 5
a D input terminal of the D flip flop is connected to the supply voltage, an input terminal of a clock is connected to an on-chip timing signal, and a Q output terminal is connected to a second input terminal of the NAND gate
Implementation Method 6
a first PMOS transistor, whose source electrode is connected to the supply voltage, a drain electrode of the first PMOS transistor being grounded through a first current source, a gate electrode of the first PMOS transistor being connected to the second component voltage
Data Source
AI summary
The present invention discloses a flash-memory low-speed read mode control circuit, which comprises a charge pump, a first voltage division circuit composed of two resistors and a first switch interconnected in series, and a second voltage division circuit composed of two capacitors interconnected in series. The first switch is used for switching between the data read mode of the low-speed read mode and the charge pump electric-leakage mode. In the data read mode, a first component voltage formed by the two resistors is fed back to the input terminal of the charge pump through a comparator, an NAND gate and a buffer, making a stable value of the output voltage of the charge pump proportional to the first component voltage. In the charge pump electric-leakage mode, the second voltage division circuit monitors the output voltage of the charge pump: when the output voltage is below a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump turned on; when the output voltage is above a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump stop working. The present invention can reduce the average current of the entire low-speed read mode significantly, and reduce the power consumption of the read process.