Non-Volatile Memory Analog Bit Storage via Current Multipliers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memory devices can only store two binary bit values, limiting their compatibility with applications requiring storage of additional bit values such as analog bit values in a continuous range of values.
Innovation Solution
The memory device employs multiple memory cells to represent each analog bit value, using unique multiplier values or addition constants to generate a unique sum value during read operations, allowing for the storage and retrieval of analog bit values by multiplying or adding to the output currents of each memory cell, enabling the storage of multiple bit values beyond the traditional binary states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional non-volatile memory devices use binary storage, then the device structure remains simple, but the storage capacity is limited to two bit values
Solution Approach 1:
The patent divides a single memory cell into multiple segments (first and second memory cells) that can be independently controlled through selective gate activation. This segmentation allows each segment to contribute to the overall output current, enabling multi-bit storage while maintaining a relatively simple physical structure. The first memory cell stores a most significant bit and the second memory cell stores a least significant bit, with different gate combinations enabling independent access to each segment.
Solution Approach 2:
The patent adds a temporal dimension to the storage system by using different gate voltage combinations at different time periods to access different memory segments. During a first time period, the first gate is activated to access the first memory cell; during a second time period, the second gate is activated to access the second memory cell. This time-multiplexed approach enables multi-bit storage without requiring all memory segments to be physically accessible simultaneously, thus avoiding increased structural complexity.
2Adaptability or versatility
If multiple memory cells are used to store analog bit values, then the storage capacity increases, but the read operation complexity increases
Solution Approach 1:
The patent merges the output currents from multiple memory cells through a current summing node. The first memory cell produces a first output current and the second memory cell produces a second output current, both of which are summed at a common node to produce a combined output signal. This merging approach simplifies the read operation by providing a single summed current output that represents the combined state of multiple memory cells, rather than requiring separate read circuits for each cell.
Solution Approach 2:
The patent implements a universal read circuit that can read multiple memory cells through a single output path. The current summing node serves as a universal interface that accepts currents from different memory segments and differentiates between them based on which gates are activated during the read operation. This multi-functional read path can handle both single-bit and multi-bit reads, as well as analog value retrieval, without requiring separate dedicated read circuits for each memory cell.
3Measurement precision
If unique multiplier values are used for each memory cell, then analog bit values can be distinguished, but the circuit complexity increases
Solution Approach 1:
The patent applies different local qualities (threshold voltage characteristics) to different memory cells through their respective control gates. The first memory cell has a first threshold voltage determined by its gate configuration, while the second memory cell has a second threshold voltage determined by its gate configuration. These locally differentiated threshold voltages act as unique identifiers for each memory cell's contribution to the summed current, enabling analog value differentiation without requiring external multiplier circuits. The local quality difference is created through the specific gate voltage combinations applied to each memory cell during the read operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the storage and retrieval of analog bit values by generating a unique sum value for each combination of program states, effectively expanding the memory device's capacity to store values beyond the traditional binary limitations, making it suitable for applications like analog neural networks.
Implementation Method 1
The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism
Implementation Method 2
Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected onto the floating gate 20 by hot-electron injection
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.