Nonvolatile Memory Mat Voltage Control
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices, such as flash memory devices operating in multi-plane mode, face challenges in reducing the load on word-lines and bit-lines, which affects their performance.
Innovation Solution
A nonvolatile memory device architecture that includes a memory cell array with multiple mats, each comprising memory blocks connected to word-lines and bit-lines, a voltage generator, a page buffer circuit, and a control circuit that differentiates voltage levels and application time intervals based on the number of mats operating simultaneously, optimizing voltage application in both single mat and multi-mat modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flash memory devices operate in multi-plane mode to improve read/write performance, then productivity is improved, but device complexity increases and word-line/bit-line load increases
Solution Approach 1:
The memory device is divided into multiple independent planes, each with its own set of word-lines and bit-lines. This segmentation allows parallel read/write operations across different planes, improving productivity while isolating the load on individual word-lines and bit-lines to manageable levels.
Solution Approach 2:
The patent introduces a plane dimension in addition to the traditional row-column structure. By operating in multiple planes simultaneously, the system achieves parallelism without increasing the complexity of individual word-lines or bit-lines, as each plane maintains its own independent addressing space.
2Productivity
If multiple mats operate simultaneously to enhance performance, then productivity is improved, but the voltage management complexity increases
Solution Approach 1:
The control circuit dynamically adjusts voltage application based on the number of simultaneously operating mats. When multiple mats operate concurrently, the control circuit modifies voltage levels and timing to prevent interference and ensure proper operation, optimizing performance while managing voltage complexity adaptively.
Solution Approach 2:
The patent changes voltage parameters (levels, timing, duration) based on the operational mode. Different voltage configurations are applied depending on whether single-mat or multi-mat operations are performed, allowing the system to maintain simplicity in each mode while achieving high performance in multi-mat mode.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.