Semiconductor Storage Device Transistor Configuration for High Density Integration
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in achieving high density integration due to limitations in transistor arrangement and wiring layout, which affects both integration density and operating speed.
Innovation Solution
The semiconductor storage device employs a configuration where both transistors in the chip CM and chip CP are used to form the transistor TBLK, allowing for appropriate division and arrangement of the transistor circuit in the Z direction, thereby facilitating high density integration in the X direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are arranged using conventional methods in existing semiconductor storage devices, then manufacturing process is simpler, but integration density in the X direction is limited
Solution Approach 1:
The patent divides the transistor arrangement into two distinct configurations: first transistors arranged in a first configuration and second transistors arranged in a second configuration. This segmentation allows each transistor type to be optimized for specific functions while achieving high overall integration density through their coordinated arrangement in the memory cell structure.
Solution Approach 2:
The patent utilizes the Z direction (vertical stacking) to arrange transistors in addition to the conventional X-Y plane arrangement. By forming memory cells with transistors stacked vertically and connecting them through word lines and bit lines, the invention achieves high density integration in the X direction while maintaining manageable complexity through systematic three-dimensional organization.
2Quantity of substance
If transistor circuit is densely arranged in the X direction, then integration density is improved, but operating speed may be degraded
Solution Approach 1:
The patent assigns different arrangement configurations to different transistor types within the memory cell. First transistors and second transistors are arranged differently based on their specific functional requirements, allowing optimal local performance for each transistor type while maintaining high overall density. This local optimization ensures that speed-critical transistors are positioned and configured for maximum performance.
Solution Approach 2:
The patent employs dynamic voltage application through word lines that can be selectively activated. The voltage application mechanism allows dynamic control of transistor operation, enabling high-speed read and write operations by activating only the necessary transistors and conductive paths, thus maintaining high operating speed despite dense integration.
3Quantity of substance
If both transistors in chip CM and chip CP are used to form transistor TBLK, then high density integration is achieved, but device complexity increases
Solution Approach 1:
The patent designs a universal memory cell structure that can accommodate multiple transistor configurations. The same basic memory cell framework supports both first transistors from chip CM and second transistors from chip CP, allowing them to work together as a unified system. This multi-functionality approach achieves high integration density while managing complexity through standardized design elements.
Solution Approach 2:
The patent integrates transistors from multiple chips (chip CM and chip CP) into a nested hierarchical structure. The first and second transistors are arranged in configurations that allow them to function as a unified transistor TBLK, with the third transistor providing additional functionality. This nesting approach achieves high density integration by efficiently utilizing space across multiple chip layers while maintaining manageable complexity through systematic organization.
Data Source
AI summary
A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.