In-Memory Matrix Multiplication Using Non-Volatile Memory Cells
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Solution Overview
Problem
Existing artificial neural networks (ANNs) face challenges in large-scale integration due to the need for additional circuitry for mathematical operations like convolution and matrix multiplication, which increases footprint and cost.
Innovation Solution
The implementation of in-memory multiplication using non-volatile memory (NVM) cells, where a gate voltage is ramped to perform multiplication operations directly within the memory, allowing for concurrent computation of matrix multiplication results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional circuitry is used for matrix multiplication operations, then computation capability is improved, but device footprint and cost increase
Solution Approach 1:
The patent merges the memory storage function with the computation function by implementing matrix multiplication directly within the memory array. The memory cells store input data and perform multiplication operations using their inherent electrical characteristics, eliminating the need for separate processing circuitry and reducing overall device footprint.
Solution Approach 2:
The memory array is designed to serve multiple functions: it acts as both the storage medium for input data and the processing unit for matrix multiplication. This multi-functionality allows the same hardware structure to perform both data retention and computational tasks, reducing the need for dedicated computation circuits.
2Productivity
If additional circuitry is used for matrix multiplication operations, then computation capability is improved, but manufacturing cost increases
Solution Approach 1:
By combining storage and computation in the same memory array structure, the patent reduces the total component count and interconnect requirements. This simplification leads to lower manufacturing costs while maintaining computation capability through in-memory processing.
3Adaptability or versatility
If memory cells are used for both storage and computation, then device integration is improved, but cell complexity increases
Solution Approach 1:
The memory cells perform computation using their own stored data and inherent electrical properties without requiring external control circuitry. The multiplication operation is executed by the memory cells themselves through voltage division and current flow, eliminating the need for additional control logic and reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and concurrent performance of matrix multiplication operations within a single integrated circuit, reducing the need for external processing and lowering costs while enhancing parallelism and power efficiency.
Implementation Method 1
A state of the NVM cell is related to a multiplication product of an input multiplicand and a multiplier stored as a threshold voltage of the NVM cell
Implementation Method 2
An input circuit coupled to a gate terminal of the non-volatile memory cell is configured to ramp a gate voltage applied to the gate terminal at a ramp rate representing a multiplicand value
Implementation Method 3
A state of the NVM cell is related to a multiplication product of an input multiplicand and a multiplier stored as a threshold voltage of the NVM cell
Data Source
AI summary
Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.