Memory Program Verify Window Adjustment
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Solution Overview
Problem
Existing non-volatile memory apparatuses face challenges in efficiently programming and verifying data states, leading to potential over-programming issues due to the verification of later data states before earlier ones have completed programming, which can result in reduced performance and increased program time.
Innovation Solution
A memory apparatus and method where memory cells connected to word lines in strings are programmed with a series of pulses followed by verification pulses, with later data states only being verified after earlier ones have finished programming, and the verification windows are adjusted based on the completion status of prior data states to prevent over-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If verification of later data states is performed before earlier data states finish programming, then programming time is reduced, but over-programming risk increases
Solution Approach 1:
The patent segments the data states into multiple groups (first data states and second data states) with different verification timing. First data states are verified after their programming completes, while second data states are verified only after first data states are fully programmed and verified. This segmentation resolves the contradiction by allowing parallel verification operations that maintain reliability while reducing overall programming time.
Solution Approach 2:
The patent implements preliminary verification of first data states before verifying second data states. This preliminary action ensures that lower threshold voltage states are stabilized before attempting to verify higher threshold voltage states, preventing over-programming while enabling more efficient verification sequencing that reduces total programming time.
2Device complexity
If all data states are verified simultaneously, then verification process is simplified, but programming precision deteriorates
Solution Approach 1:
The patent segments verification into sequential stages: first verifying first data states (with lower threshold voltages) after their programming completes, then verifying second data states (with higher threshold voltages) only after first data states are confirmed. This segmented approach maintains precision by ensuring each state is verified at the appropriate time while keeping the control logic manageable through structured sequencing.
Solution Approach 2:
The patent dynamically adjusts verification timing based on programming completion status. The verification process adapts its sequence based on which data states have finished programming, allowing flexible verification ordering that maintains precision without requiring complex simultaneous verification mechanisms.
Data Source
AI summary
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.