Low Latency Flash Memory Erase Suspend via Over-Erased Cell Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face issues with over-erased memory cells causing leakage during erase operations, leading to failed read operations and increased latency in correcting these cells, which existing methods attempt to address with negative voltage application but at the cost of increased die area and complexity.
Innovation Solution
A nonvolatile memory array with control logic that partitions memory cells into sectors, applies an erase bias to reduce threshold voltages, identifies over-erased cells, and uses a low-latency correction pulse to increase their threshold voltages, allowing for efficient erase suspend operations without significant die size or cost increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a soft program sequence is performed to correct over-erased memory cells before suspending the erase operation, then the leakage from over-erased cells is reduced, but the latency time increases to one to a few milliseconds
Solution Approach 1:
The patent identifies over-erased memory cells during the erase verify sequence before the soft program sequence is executed. By detecting which cells are over-erased in advance and suspending the erase operation at this point, the system can quickly respond to suspend commands without needing to complete the full soft program sequence, thereby reducing latency while still addressing the leakage issue when suspend is required.
Solution Approach 2:
The erase verify sequence automatically identifies over-erased cells during the normal erase operation flow. This self-identification mechanism eliminates the need for separate detection circuits or additional verification steps when suspend is commanded, allowing the system to quickly determine which cells need correction and respond to suspend commands with minimal delay.
2Loss of time
If negative voltage is applied to reduce leakage from over-erased memory cells, then the latency time is reduced, but the die area and cost increase due to negative voltage pump circuits
Solution Approach 1:
The patent extracts the negative voltage pump circuits from the system by using an alternative approach: suspending the erase operation after over-erased cells are identified during the erase verify sequence. This eliminates the need for complex negative voltage generation hardware while still achieving low-latency response to suspend commands through the soft program sequence mechanism.
Solution Approach 2:
Instead of implementing expensive negative voltage pump circuits, the patent uses a simpler, lower-cost approach based on standard erase verify and soft program sequences that are already part of the flash memory controller's normal operation. This disposable-like approach uses existing circuitry in a clever sequence rather than adding permanent complex hardware.
3Loss of time
If the erase operation is suspended without correcting over-erased cells, then the latency time is reduced, but read operations on other memory cells may fail due to leakage current
Solution Approach 1:
The patent performs preliminary identification of over-erased cells during the erase verify sequence before suspend is commanded. This preliminary action allows the system to know which cells are problematic, and when suspend is commanded, it can quickly execute a targeted soft program sequence only for those identified cells, rather than waiting for the full erase cycle or using complex real-time correction mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage from over-erased memory cells with low latency, meeting the erase suspend command requirements while minimizing die area and cost, thus enhancing the operational efficiency of flash memory devices.
Implementation Method 1
Data can be erased from a flash memory cell by applying erase voltage pulses to the flash memory cell, causing charge to be removed from the charge storage structure of the cell
Implementation Method 2
Data is stored in a memory cell of a flash memory device by controlling the amount of charge stored in the charge storage structure. The amount of stored charge sets a threshold voltage for the memory cell
Data Source
AI summary
A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.