Memory Page Buffer Source Side Sensing Noise Reduction
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Solution Overview
Problem
Noise and reduced sensing margins in memory architectures, particularly in multi-level cell memory, due to high bit line current during read operations, which can lead to sensing failure.
Innovation Solution
A memory method and device that applies a read bias arrangement to a second memory cell without discharging the bit line, precharges the bit line, and uses a sequence of increasingly larger magnitude voltages to the gate of the second memory cell, along with a differential sense amplifier, to improve sensing accuracy and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read operation is performed on a memory cell with high gate voltage, then the read operation can be completed, but high bit line current is generated causing noise and reduced sensing margins
Solution Approach 1:
The bit line is precharged to a first voltage level before the read operation. This preliminary action ensures that the bit line is already at the appropriate voltage state, allowing the read operation to proceed without generating excessive current transients that would cause noise and reduce sensing margins.
Solution Approach 2:
The gate voltage is applied in a controlled sequence of increasing magnitude levels rather than as a single high voltage. This parameter change approach allows the memory cell to be read step-by-step, preventing sudden large current spikes on the bit line while still achieving complete read of the data.
2Device complexity
If source side sensing is used, then the memory architecture can be simplified, but the signal amplitude becomes significantly smaller reducing sensing performance
Solution Approach 1:
The bit line is precharged to a specific voltage level before the read operation. This preliminary conditioning of the bit line enhances the signal amplitude that will be sensed during the read operation, compensating for the inherently smaller signal amplitudes produced by source side sensing architecture.
3Quantity of substance
If multi level cell memory architecture is used, then storage density is increased, but the large difference in gate voltage magnitudes causes high bit line current and sensing difficulties
Solution Approach 1:
The gate voltage is applied in a controlled sequence of increasing magnitude levels rather than as a single high voltage. This parameter change approach allows the memory cell to be read step-by-step, preventing sudden large current spikes on the bit line while still achieving complete read of the data.
Solution Approach 2:
The bit line is precharged to a first voltage level before the read operation. This preliminary action ensures that the bit line is already at the appropriate voltage state, allowing the read operation to proceed without generating excessive current transients that would cause noise and reduce sensing margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances sensing accuracy by reducing bit line coupling noise and voltage drop, thereby improving sensing margins and preventing sensing failures in multi-level cell memory architectures.
Implementation Method 1
reads a data value on the second memory cell based on whether current flows from a source line of the second memory cell to the bit line coupled to the second memory cell
Implementation Method 2
The read bias arrangement causes the current to flow through a diode between the source line and the bit line. The diode prevents the current from flowing from the bit line to the source line.
Implementation Method 3
the read bias arrangement reads the data value with a differential sense amplifier
Data Source
AI summary
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.