Semiconductor Memory Device Program Verification Accuracy
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Solution Overview
Problem
Current semiconductor memory devices face accuracy issues in program verification, particularly with the current sensing method, which deteriorates with increasing device capacity and fine processes, necessitating a more precise method to count failed memory cells in a rapid time frame.
Innovation Solution
Incorporating a sensing circuit and a fail checking circuit within the semiconductor memory device to enhance the accuracy of program verification by outputting pass/fail signals and controlling the program operation based on verifying result signals, thereby reducing the number of sensed fail bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a current sensing method is used for program verification, then the verification speed is improved, but the measurement precision deteriorates
Solution Approach 1:
The patent divides the memory cell array into multiple regions and performs program verification on each region separately rather than sensing all memory cells simultaneously. This segmentation allows the system to maintain rapid verification speed while improving measurement precision by reducing the error range associated with sensing large numbers of cells in parallel. The verification is performed in multiple passes, each handling a subset of the total memory cells.
Solution Approach 2:
The patent performs program verification multiple times on different regions of the memory cell array, conducting more verification operations than a single comprehensive sensing would require. By verifying partial regions repeatedly and aggregating the results, the system achieves both rapid verification speed and improved accuracy in counting failed memory cells.
2Quantity of substance
If the capacity of semiconductor memory device increases, then the device functionality is improved, but the measurement precision of program verification deteriorates
Solution Approach 1:
The patent addresses the accuracy deterioration in high-capacity devices by segmenting the large memory cell array into multiple smaller regions. Each region is verified separately through program verification operations, allowing the system to maintain accurate counting of failed memory cells even when the total device capacity is large. This regional approach prevents the error range from expanding proportionally with device capacity.
3Productivity
If program verification is performed in rapid time period, then the productivity is improved, but the measurement precision deteriorates
Solution Approach 1:
The patent divides the program verification process into multiple rapid passes over segmented regions of the memory cell array. Each pass verifies a subset of memory cells quickly, and the results are aggregated to determine the total number of failed cells. This segmented approach maintains high productivity while improving measurement precision by reducing the error range in each individual sensing operation.
Solution Approach 2:
The patent performs multiple verification passes on different regions, conducting more verification operations than a single comprehensive check would require. This partial verification approach performed repeatedly achieves both rapid verification throughput and improved accuracy in fail bit counting by aggregating results from multiple rapid measurements.
Data Source
AI summary
A semiconductor memory device of the present invention includes a memory cell array configured to include a sensing circuit configured to perform program verifying of the page buffer group selected by the select signal, and configured to output a pass/fail signal corresponding to the page buffer group, a verifying result signal generation section configured to output one or more of a first verifying signal and a second verifying signal in accordance with pass or fail of the program for total page buffer groups by using the pass/fail signal, and a control circuit configured to output the select signals to verify the program after the program is performed, and control operation of the program in response to an output signal of the verifying result signal generation section.