CFET Power Rail Tap Structure for Dense Logic Cell Layouts
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Solution Overview
Problem
Existing CFET devices face challenges in routing power supply from buried power rails to top transistor structures, leading to area penalties and reduced logic cell density due to the need for dedicated tap cells.
Innovation Solution
The CFET structure incorporates a power rail below the first transistor structure and a power routing line above the second transistor structure, connected via a tap connection structure that bypasses the first transistor structure, allowing for efficient power supply to top transistor structures without dedicated tap cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated tap cells are used to connect backside power supply to local power supply, then power supply to top transistor structures is achieved, but device area increases significantly (4-5% area penalty)
Solution Approach 1:
The patent combines the power routing function with existing transistor structures by using the source/drain structures of top transistors as part of the power distribution network. The backside power rail connects directly to these source/drain structures, eliminating the need for separate dedicated tap cells while maintaining full power supply functionality.
Solution Approach 2:
The source and drain structures of the top transistor structures serve dual purposes: they function as both the active transistor components for logic operations and as the power distribution pathways. This multi-functionality allows the same structures to handle both signal processing and power delivery, removing the requirement for dedicated power-only tap cells.
2Reliability
If dedicated tap cells are arranged in regular columns to cover the whole height of the chip, then power supply connectivity is ensured, but the total number of usable CFET logic cells is reduced
Solution Approach 1:
The power distribution function is merged into the logic cell structures themselves. By using the source/drain structures of top transistors as power distribution pathways, the patent eliminates the need for separate dedicated tap cells, thereby increasing the density of usable logic cells while maintaining full power supply connectivity.
Solution Approach 2:
The patent extracts the power distribution function from dedicated tap cells and integrates it directly into the top transistor structures. This extraction eliminates the separate tap cell component, allowing all cell positions to be used for logic functions while still providing comprehensive power supply coverage.
3Reliability
If power supply is routed from backside power rail to top transistor structures, then power delivery is achieved, but routing complexity increases
Solution Approach 1:
The patent merges the power routing function with the existing transistor source/drain structures. By using these structures as dual-purpose components for both logic operation and power distribution, the routing complexity is minimized while ensuring reliable power delivery to all top transistor structures.
Solution Approach 2:
The top transistor structures serve themselves by using their own source/drain structures as the power distribution pathways. This self-service approach eliminates the need for complex external routing networks, as the structures that need power already contain the pathways for its delivery.
Data Source
AI summary
The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure which is arranged above the first transistor structure and which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure of the at least one CFET element, and a power routing line arranged above the second transistor structure of the at least one CFET element. The power routing line is electrically connected to the source and/or drain structure of the second transistor structure from the top. The at least one CFET element further has a tap connection structure which is arranged to electrically connect the power rail with the source and/or drain structure of the second transistor structure. The tap connection structure is arranged to bypass the first transistor structure on one side.