CFET Superlattice Release Layers for Strain-Preserving Etch Selectivity
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Solution Overview
Problem
Existing CFET transistors face challenges with reduced drive current due to strain and mobility issues caused by high germanium content in sacrificial layers, leading to poor transistor performance.
Innovation Solution
A vertically stacked superlattice structure is implemented, comprising alternating layers of silicon nanosheet channel layers and doped silicon germanium nanosheet release layers, with a sacrificial layer having a germanium content between 0% to 50% for improved etch selectivity and reduced defect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the middle sacrificial layer comprises SiGe with a high concentration of Ge to achieve etch contrast, then etch selectivity is improved, but the superlattice relaxes causing strain and mobility reduction
Solution Approach 1:
The patent applies local quality by differentiating the Ge concentration in different layers: the sacrificial layer has high Ge content (40-70%) for etch selectivity, while the release layers have low Ge content (0-20%) to maintain superlattice strain and prevent relaxation. This localized material composition optimization resolves the contradiction between etch selectivity and transistor performance.
Solution Approach 2:
The patent changes the Ge concentration parameter across different layers to achieve both objectives. By varying the Ge content from high in the sacrificial layer to low in the release layers, the patent simultaneously achieves high etch selectivity and maintains the strained superlattice structure necessary for good transistor performance.
2Reliability
If the superlattice is fully strained to improve drive current and mobility, then transistor performance is enhanced, but the release layers become difficult to selectively remove
Solution Approach 1:
The patent maintains low Ge content (0-20%) in the release layers to preserve superlattice strain and improve transistor performance, while keeping the sacrificial layer with high Ge content (40-70%) for easy selective removal. This localized composition differentiation allows both objectives to be achieved simultaneously.
3Manufacturing precision
If the germanium content in sacrificial layer is increased to improve etch contrast, then selective removal is improved, but defect formation in channel layers increases
Solution Approach 1:
The patent locally optimizes Ge content: high Ge (40-70%) in the sacrificial layer provides excellent etch contrast, while low Ge (0-20%) in the release layers prevents defect formation in the channel layers. This spatial differentiation of material composition resolves the contradiction between etch contrast and channel layer quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a fully strained superlattice structure with reduced defect formation in channel layers, enhancing drive current and mobility while allowing for selective removal of the sacrificial layer without damaging the release layers.
Implementation Method 1
The nanosheet release layer comprises doped silicon germanium (SiGe)
Data Source
AI summary
Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).