CFET Standard-Cell Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing downsizing of integrated circuits poses challenges for standard cells, leading to issues such as high parasitic capacitance and degraded performance due to the proximity of input and output metal lines in standard cells.
Innovation Solution
The use of Complementary Field-Effect Transistors (CFETs) with double-height design separates input and output metal lines, reducing parasitic capacitance and improving performance by allowing for shorter signal paths and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cells are downsized to increase integration density, then more cells can be placed on a chip, but parasitic capacitance between input and output metal lines increases and performance degrades
Solution Approach 1:
The patent transitions from a planar (2D) arrangement of metal lines to a three-dimensional (3D) stacked configuration by placing input and output metal lines on different vertical levels. This vertical separation in the third dimension reduces parasitic capacitance between lines while maintaining compact footprint for high integration density.
Solution Approach 2:
The standard cell is divided into multiple height segments (single-height and double-height cells) with different vertical arrangements of metal lines. This segmentation allows optimization of parasitic capacitance in critical paths while maintaining integration density in other regions.
2Area of stationary object
If input and output metal lines are placed close together to reduce cell size, then integration density increases, but signal path length increases and resistance increases
Solution Approach 1:
The patent uses vertical stacking to separate input and output metal lines on different levels, allowing short horizontal connections within the same cell while avoiding long lateral routes. This 3D arrangement reduces signal path length without increasing cell area.
3Manufacturing precision
If standard cells are designed with fixed height to simplify manufacturing, then manufacturing precision is maintained, but flexibility to optimize performance for different circuits is reduced
Solution Approach 1:
The patent segments standard cells into different height categories (single-height and double-height) while maintaining consistent manufacturing processes for each segment. This allows performance optimization through height selection without requiring complex variable-height manufacturing.
Solution Approach 2:
The patent changes the discrete parameter of cell height (1x or 2x) to optimize performance for different circuit configurations. This parameter variation is achieved through standardized manufacturing processes that can reliably produce both height types.
Data Source
AI summary
A structure includes a standard cell, which includes a first single-height part and a second single-height part. The first single-height part comprises a first VDD line, a first VSS line, and a first input metal line. The second single-height part is abutting the first single-height part to form an interface. The second single-height part comprises a second VDD line, a second VSS line, and an output metal line. In a top view of the structure, the first input metal line and the output metal line have lengthwise directions parallel to the interface.