CFET Standard Cell Layout for Semiconductor Integration Density
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Solution Overview
Problem
The scaling down of transistors in semiconductor integrated circuits has led to increased off-current and power consumption, which results in variations in performance, reliability degradation, and yield decrease due to unevenness in layout pattern density and surrounding pattern shapes.
Innovation Solution
A semiconductor integrated circuit device with a standard cell layout structure that includes three-dimensional transistors, where redundant local interconnects overlap power supply lines, reducing density unevenness and variations in wiring pattern shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are scaled down to improve integration degree, then device density increases, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from planar two-dimensional transistors to three-dimensional vertically stacked transistors. This dimensional change allows multiple transistor layers to be stacked above each other, increasing integration density while maintaining better control over off-current through the vertical architecture and reduced leakage paths compared to continued planar scaling.
2Area of moving object
If layout pattern density is increased through scaling, then integration degree improves, but density unevenness increases causing performance variations
Solution Approach 1:
By stacking transistors vertically in three dimensions, the patent achieves higher integration without further reducing the lateral footprint of individual transistor units. This maintains more uniform layout pattern density across the substrate, reducing manufacturing variations and performance deviations caused by density unevenness.
Solution Approach 2:
The patent combines multiple transistor functions into vertically stacked units within a compact footprint. This merging approach increases integration density while maintaining uniform distribution of functional blocks across the substrate, reducing the impact of local density variations on overall circuit performance.
3Area of moving object
If transistor size is reduced to increase integration, then device density improves, but surrounding pattern shape variations increase
Solution Approach 1:
The vertical stacking architecture allows transistors to be arranged in a more regular, predictable grid pattern in the lateral plane, while depth direction provides additional integration capacity. This reduces variability in surrounding pattern shapes and improves performance predictability compared to continued lateral scaling.
Data Source
AI summary
A layout structure of a standard cell using a complementary FET (CFET) is provided. First and second transistors that are three-dimensional transistors lie between first and second power supply lines as viewed in plan, the second transistor being formed above the first transistor in the depth direction. A first local interconnect is connected with the source or drain of the first transistor, and a second local interconnect is connected with the source or drain of the second transistor. The first and second local interconnects extend in the Y direction, overlap each other as viewed in plan, and both overlap the first and second power supply lines as viewed in plan.