Chained Programmable Delay Elements for Flexible FPGA Clock Skew
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a trade-off between clock skewing flexibility and silicon area, as programmable delay elements (PDEs) must balance providing a wide range of delay values for individual Flip-Flops while minimizing area by amortizing shared delay elements with limited programmable values.
Innovation Solution
The implementation of a chaining mechanism for PDEs, utilizing a chain of delay elements and multiplexers to generate multiple skewed clocks, allowing for a higher number of discrete delay values and maximum delay values, while amortizing the area cost by sharing chained PDEs across multiple clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each Flip-Flop has its own PDE with a wide range of programmable delay values, then clock skewing flexibility is improved, but silicon area increases
Solution Approach 1:
Multiple PDEs are merged into a single shared resource that can be dynamically allocated to different Flip-Flops. The merged PDE structure uses multiplexers to switch between different delay elements, allowing one physical PDE to serve multiple FFs while maintaining flexible clock skewing capability.
Solution Approach 2:
The PDE structure is designed to be universal and multi-functional, where a single PDE can provide delay services to multiple Flip-Flops. The delay elements and multiplexers are configured to handle different clock skewing requirements for various FFs, making the PDE a universal resource rather than a dedicated component for each FF.
2Area of stationary object
If PDEs are amortized so that many FFs share them with only a few carefully chosen programmable delay values, then silicon area is reduced, but clock skewing flexibility deteriorates
Solution Approach 1:
The PDE structure incorporates dynamic switching capabilities through multiplexers that can select between different delay elements based on the specific clock skewing requirements. This dynamic configuration allows the system to adapt to different timing needs of various Flip-Flops while sharing the same physical delay resources, thereby maintaining flexibility despite area constraints.
Solution Approach 2:
The patent introduces an additional dimension of control through the multiplexer selection mechanism. Instead of only varying delay values, the system adds a selection dimension where different delay elements can be chosen for different FFs, effectively increasing the degrees of freedom for clock skewing control without proportionally increasing area.
Data Source
AI summary
Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.