Chained Programmable Delay Elements for FPGA Clock Skew Range
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a trade-off between clock skewing flexibility and silicon area, as programmable delay elements (PDEs) must balance providing a wide range of delay values for individual Flip-Flops while minimizing area by amortizing PDEs across multiple Flip-Flops, limiting the number of discrete skew values and maximum delay achievable.
Innovation Solution
The solution involves chaining programmable delay elements (PDEs) to create a chain of delay elements, using multiplexers to select among input clocks and outputs from other PDEs, allowing for a higher number of discrete delay values and increased maximum delay values, while sharing the cost of multiple PDEs across clock lines, thereby enhancing clock flexibility and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each Flip-Flop has its own PDE with a wide range of programmable delay values, then clock skewing flexibility is improved, but silicon area increases
Solution Approach 1:
The PDE is designed to serve multiple Flip-Flops simultaneously by providing a shared delay mechanism that can be selectively applied to different FFs. The multiplexer network allows a single PDE to control clock skew for multiple destination FFs, making the delay element universal rather than dedicated to a single FF.
Solution Approach 2:
The PDE functionality is segmented into shared delay elements and selective multiplexer networks. Instead of having complete PDE functionality at each FF, the delay generation is separated from the selection logic, allowing multiple FFs to share the same delay elements while maintaining individual control through multiplexers.
2Area of stationary object
If PDEs are amortized so that many FFs share them, then silicon area is reduced, but the number of discrete skew values and maximum delay achievable is limited
Solution Approach 1:
The patent extends the delay range by chaining PDEs in series, creating a multi-stage delay structure. Each PDE in the chain contributes additional delay stages, effectively multiplying the total number of discrete delay values available. This dimensional extension from single-stage to multi-stage delay achieves higher resolution without proportionally increasing area.
Solution Approach 2:
Multiple PDEs are nested in a chained configuration where the output of one PDE feeds into the input of the next. This nesting allows the delay functionality of multiple PDEs to be combined, creating a hierarchical delay structure that provides fine-grained control over clock skew while sharing resources efficiently.
3Area of stationary object
If PDEs are amortized across multiple FFs, then silicon area is reduced, but maximum delay achievable is limited
Solution Approach 1:
The maximum delay is extended by adding temporal dimensions through chained PDE stages. Each stage in the chain contributes additional delay capacity, allowing the system to achieve maximum delays that would require much larger single-stage PDEs, thereby reducing area while maintaining or extending delay range.
Solution Approach 2:
The nested chain of PDEs allows each subsequent PDE to build upon the delay capability of previous stages. This nested architecture enables the system to achieve cumulative delay effects where the total maximum delay is the sum of individual PDE delays, providing extended delay range with amortized area cost.
Data Source
AI summary
Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.