Chained Hardware Instructions for Data Stream Processing
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Solution Overview
Problem
Existing computer systems that utilize hardware acceleration circuits face increased complexity and power consumption due to the need for multiple calls to operating system libraries for specialized operations, which can lead to reduced performance.
Innovation Solution
A method where a single call to a library function specifies flags and operations on multiple data streams, generating chained hardware instructions that are executed by the hardware acceleration circuit, reducing the need for memory access and power consumption by performing operations in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple calls to operating system library functions are used for specialized operations on data streams, then the operations can be performed using hardware acceleration circuits, but the software complexity and power consumption increase
Solution Approach 1:
The patent combines multiple separate library function calls into a single unified call that processes multiple data streams simultaneously. The hardware acceleration circuit receives one call containing identifiers for multiple data streams and performs operations on all of them in parallel, eliminating the need for multiple sequential calls and reducing software complexity.
Solution Approach 2:
The hardware acceleration circuit is designed to handle multiple different operations on multiple different data streams through a single unified interface. A single library function call can specify various operations (e.g., encryption, compression, filtering) on various data streams, making the system more versatile and reducing the number of specialized function calls needed.
2Productivity
If multiple calls to operating system library functions are used for specialized operations, then hardware acceleration can be utilized, but power consumption increases due to repeated memory access
Solution Approach 1:
By merging multiple operations into a single call, the system reduces the frequency of memory access events. The hardware acceleration circuit processes multiple data streams in parallel within one operation cycle, eliminating the need for repeated memory access that would occur with multiple sequential calls, thereby reducing power consumption.
Solution Approach 2:
The hardware acceleration circuit maintains continuous operation by processing multiple data streams in parallel without interruption. Instead of stopping and restarting for each separate operation call, the circuit continuously processes streams based on identifiers provided in the single call, reducing idle cycles and associated power consumption.
3Productivity
If multiple separate calls are made to process different data streams, then each operation can be executed, but the overall execution time and system performance are reduced
Solution Approach 1:
The patent segments the processing of multiple data streams into parallel independent operations within a single call. Each data stream is identified by a unique identifier and processed independently but simultaneously by the hardware acceleration circuit, allowing parallel execution that reduces total execution time compared to sequential processing.
Solution Approach 2:
Multiple data stream processing operations are merged into a single unified call that executes in parallel. The hardware acceleration circuit receives one call with multiple stream identifiers and processes all streams simultaneously, reducing the total execution time from the sum of individual sequential operations to approximately the time of the longest single operation.
Data Source
AI summary
A method for accessing and using a hardware acceleration circuit in a computer system is disclosed. The computer system may receive a single call to a particular library function that is implemented by a hardware acceleration circuit included in the computer system. A plurality of chained hardware instructions is generated in response to the single call, wherein the plurality of chained hardware instructions is based on different ones of a plurality of flags and a plurality of data streams specified by the single call. The computer system may send the plurality of chained hardware instructions to the hardware acceleration circuit for execution.