Programmable Chalcogenide Capacitors Without CMOS Array Complexity
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Solution Overview
Problem
Existing capacitor technologies, such as CMOS programmable capacitor arrays, are complex, costly, and difficult to scale due to their two-dimensional structure and reliance on CMOS transistors, limiting their ability to dynamically configure capacitance and occupy more space than necessary.
Innovation Solution
The use of chalcogenide materials as dielectric in capacitors, allowing for dynamic capacitance configuration through programming pulses that alter the material's crystallinity, enabling a three-dimensional array with reduced complexity and cost by eliminating the need for CMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS programmable capacitor arrays are used to dynamically configure capacitance, then capacitance configurability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies parameter changes by utilizing the phase transition properties of chalcogenide materials. By changing the physical state of the chalcogenide material between crystalline and amorphous phases through applied voltage or current, the capacitance value can be dynamically adjusted. This eliminates the need for complex CMOS transistor switching networks while achieving programmable capacitance configuration.
Solution Approach 2:
The patent replaces the mechanical/electronic switching system (CMOS transistors) with a material-based system. Instead of using active electronic components to switch capacitors in and out of the circuit, the invention uses the intrinsic phase change properties of chalcogenide materials to achieve capacitance modulation, thereby simplifying the device architecture.
2Adaptability or versatility
If CMOS programmable capacitor arrays are used to dynamically configure capacitance, then capacitance configurability is improved, but manufacturing cost increases
Solution Approach 1:
The patent utilizes parameter changes in the material phase to achieve capacitance configuration. The chalcogenide material can be transitioned between crystalline and amorphous states through simple voltage or current application, enabling programmable capacitance without requiring complex manufacturing processes or expensive CMOS transistor fabrication.
Solution Approach 2:
The patent employs chalcogenide materials that can be easily deposited using conventional thin-film techniques, replacing the need for expensive CMOS transistor fabrication. The material's phase change properties provide the necessary functionality at a lower manufacturing cost, making the system more economically viable.
3Adaptability or versatility
If two-dimensional CMOS capacitor arrays are used, then capacitance configuration is achieved, but area occupancy increases
Solution Approach 1:
The patent transitions from a two-dimensional array architecture to a three-dimensional structure by stacking multiple capacitor layers vertically. This dimensional change allows for significantly higher capacitance density within the same footprint area, as capacitors can be arranged in multiple layers rather than spread out in a single plane.
Solution Approach 2:
The patent implements nested structures by stacking capacitor layers one on top of another, with shared electrode structures. This nesting approach allows multiple capacitor elements to occupy the same lateral footprint by utilizing the vertical dimension, thereby reducing the overall area occupancy while maintaining capacitance configuration capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a compact, cost-effective, and scalable solution to dynamically configure capacitance, enhancing the density and efficiency of energy storage in electronic devices without the drawbacks of traditional CMOS arrays.
Implementation Method 1
A controller may apply a first voltage to the first electrode and the second electrode to cause the chalcogenide material to change from a first phase to a second phase
Implementation Method 2
A programming pulse (e.g., an electrical pulse) may be applied to the chalcogenide capacitor, which may change a physical property of the chalcogenide material (e.g., increasing or decreasing a crystallinity of the chalcogenide material) thereby adjusting a capacitance of the chalcogenide capacitor
Implementation Method 3
A capacitor may have a capacitance, which may indicate an ability of the capacitor to store a voltage
Data Source
AI summary
Methods, systems, and devices for programmable chalcogenide capacitors are described. A first programming pulse may be applied, for a first duration, to a capacitor comprising a chalcogenide material to adjust a capacitance of the capacitor from a first capacitance to a second capacitance. A pulse may be applied to the capacitor based on applying the first programming pulse to the capacitor. A first voltage may be stored in the capacitor based on adjusting the capacitance of the capacitor from the first capacitance to the second capacitance, and the first voltage may be stored based on the capacitor having the second capacitance.


