Capacitor Material Over Channel Regions for Higher Capacitance Density
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Solution Overview
Problem
As semiconductor devices are scaled down, the device capacitance per footprint decreases, requiring more area for capacitors in advanced process nodes, making it challenging to maintain capacitance while reducing transistor size.
Innovation Solution
The implementation of a deposited capacitor material (DCM) layer directly on the semiconductor channel, coupled with a high-k metal gate stack, increases the coupling area and capacitance by fully surrounding the metallic gate electrode, thereby enhancing capacitance per device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is scaled down to increase functional density, then production efficiency increases and costs decrease, but device capacitance per footprint decreases requiring more area for capacitors
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertically-coupled capacitor structures. The capacitor is formed by depositing capacitor material over the channel region of an underlying transistor, creating vertical stacking that increases capacitance per footprint area and resolves the contradiction between device scaling and capacitor area requirements
Solution Approach 2:
The patent makes the transistor channel region serve dual functions: as the active channel for transistor operation and as the base structure for forming the capacitor. The capacitor material deposited over the channel region creates a structure that provides both transistor functionality and capacitor functionality, increasing capacitance per footprint without requiring separate dedicated capacitor area
2Productivity
If device geometry is scaled down, then functional density increases, but capacitance per footprint decreases
Solution Approach 1:
The patent creates vertical stacking of capacitor material over the transistor channel, transitioning from two-dimensional planar capacitance to three-dimensional volumetric capacitance. This vertical dimension increases the quantity of capacitor material per footprint area, thereby increasing total capacitance while maintaining high functional density
Solution Approach 2:
The capacitor structure is nested within and over the transistor structure. The capacitor material is deposited directly over the channel region, creating a nested configuration where the capacitor encompasses the transistor channel, maximizing space utilization and increasing capacitance per footprint
3Quantity of substance
If vertically-coupled capacitor structures are formed over channel regions, then capacitance per footprint increases, but process complexity increases
Solution Approach 1:
The patent merges the capacitor formation process with the existing transistor fabrication process. The capacitor material is deposited using the same deposition equipment and processes already used for gate dielectric and metal gate formation, combining multiple functions into a single integrated process flow and reducing overall process complexity
Solution Approach 2:
The transistor channel region automatically serves as the base structure for capacitor formation. The existing channel region definition and dimensions directly determine the capacitor geometry, eliminating the need for separate capacitor patterning and definition steps, thereby reducing process complexity while maintaining high capacitance per footprint
Data Source
AI summary
A method includes providing first and second structures over a substrate, wherein each of the first and second structures includes source/drain (S/D) regions, a channel region between the S/D regions, a sacrificial dielectric layer, and a sacrificial gate. The method further includes partially recessing the sacrificial gate without exposing the sacrificial dielectric layer in each of the first and the second structures; forming a first patterned mask that covers the first structure; removing the sacrificial gate from the second structure; removing the first patterned mask and the sacrificial dielectric layer from the second structure; and depositing a layer of a capacitor material over the portion of the sacrificial gate in the first structure and over the channel region in the second structure.