Channel Control Circuit for Flash Memory Read Efficiency

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Solution Overview

Problem

Existing storage device control circuits face challenges in dynamically adjusting the data output order of multiple channels, which affects the efficiency of data reading from flash memory.

Innovation Solution

A channel controlling device comprising a multiplexing circuit, a sorting circuit, and an arbitration circuit that selects and sorts digital numbers to determine the output order of channels, allowing for dynamic adjustment and correction of data output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple channels are used to increase read speed, then data reading efficiency is improved, but the complexity of controlling data output order increases

Engineering Contradiction:
Improvedata reading efficiencyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit is segmented into three functional modules: multiplexing circuit for channel selection, sorting circuit for order management, and arbitration circuit for conflict resolution. This segmentation allows each module to handle specific tasks independently, improving overall control efficiency while maintaining manageable complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sorting circuit acts as an intermediary between the multiplexing circuit and the decoder, managing the data output order from multiple channels. It receives channel data selection signals, sorts them according to predetermined digital numbers, and outputs sorted signals to the arbitration circuit, thereby mediating the complex multi-channel control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the output order is dynamically adjustable, then data reading accuracy is improved, but the response time for correction increases

Engineering Contradiction:
Improvedata output order accuracyVSAvoidcorrection response time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The sorting circuit is pre-configured with predetermined digital numbers that define the correct output order for multiple channels. This preliminary setup allows the arbitration circuit to quickly determine the correct channel selection without complex real-time calculations, enabling fast correction when output order errors occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The arbitration circuit continuously monitors the data output order and compares it with the predetermined correct order. When an error is detected, the feedback mechanism triggers immediate correction by adjusting the channel selection signal through the sorting circuit, ensuring both accuracy and rapid response time.

Inventive Principle:
Principle #23Feedback

3Reliability

If arbitration circuit instantly corrects output order, then data reading reliability is improved, but the device complexity increases

Engineering Contradiction:
Improvedata reading reliabilityVSAvoidarbitration circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration circuit implements dynamic correction capability by continuously monitoring channel output orders and instantly adjusting the selection signal when errors are detected. This dynamic operation ensures high data reading reliability while the modular design keeps the circuit complexity manageable through clear functional separation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9940983B2Channel controlling device for improving data reading efficiency
Publication Date: 2018.04.10 SILICON MOTION INC
  • US9940983B2 patent drawing
  • US9940983B2 patent drawing
  • US9940983B2 patent drawing

AI summary

A channel controlling device includes: a multiplexing circuit coupled to multiple channels for selecting a particular channel from the channels to output a channel data according to a selection signal, wherein the channels correspond to multiple predetermined digital numbers; a sorting circuit arranged to sort the predetermined digital numbers to form multiple sorted digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selection signal according to the plurality of sorted digital numbers.