Digital Storage TRIZ Cases

A magnetic device uses segmented regions and an intermediate portion to control magnetization via spin transfer torque.

A memory system uses test circuits to identify weakest cells and substitute redundant columns for reliable low-voltage operation.

Dual data-dependent busses segment memory arrays to relax decoder voltage demands, reducing leakage current in unselected cells.

A sub-word line driver uses a common gate boosted voltage circuit to reduce semiconductor substrate area.

Polarity swapping circuitry inverts bitline connections to alternate storage states, reducing aging degradation in SRAM and write current stress in MRAM.

Dynamic voltage control in an RRAM sense module prevents read disturbance while maintaining fast access times.

A composite pull-up driver merges PMOS and NMOS transistors to enhance output slew rate via level-shifted pre-control signals.

Calibrating variable resistors sets reference levels between resistance distributions, improving sensing accuracy at elevated temperatures.

A ferroelectric capacitor cell structure retains electric charge through polarization reversal for extended periods.

Merged scan flip flops serialize state data into memory units, eliminating complex power supply routing and reducing chip area overhead.

A read circuit generates bias current by combining reference and compensation currents to maximize the read margin in resistive memory cells.

A controller adjusts signal delay time using a ring oscillator and look-up table to maintain circuit timing accuracy.

Segmenting write and read transistors resolves the trade-off between high threshold voltage requirements and slow sensing speeds in flash memory.

A compensatory memory system uses a control block to adapt circuit timings via dynamic delay adjustment.

A content addressable memory uses a power control circuit to selectively disable comparison circuits based on valid data presence.

A leakage testing method for DRAMs with recess gates uses word line disturbance to identify failure types.

A memory system performs self-refresh operations using internal logic to conserve power.

Dynamic pulse width control in semiconductor memory devices prevents operation errors by extending main strobe signals during high-speed bank grouping access.

Memory controller tailors refresh rates per bank based on retention profiles, reducing power consumption while maintaining data integrity.

A quasi-differential read circuit charges bit line pairs at distinct rates to generate a differential voltage for accurate state detection.

Sequential memory component activation lowers peak power and heat generation, enabling smaller voltage regulators.

A resistive memory programming circuit applies incremental voltage pulses to adjust cell resistance toward a target state.

A method controls current path range by applying an electric field to a spontaneous polarization active layer through an application electrode.

Dynamic bit line capacitor adjustment allows high-speed DRAM operation while maintaining non-volatile FRAM storage, resolving speed-reliability trade-offs.

A memory controller limits co-pending consolidated activation commands to optimize resource usage in DRAM systems.

A memory core circuit counts word line activations to identify frequently accessed lines for targeted refresh operations.

Bit line driver charges conductors to a reduced voltage level using transistor threshold characteristics.

Selective refresh operations prevent data drift in phase change memory by equalizing cell resistance while minimizing power consumption.

Integrated electro-optic devices use evanescently coupled double-ring resonators to convert microwave signals into optical carriers with high modulation efficiency.

A channel controlling device uses multiplexing and sorting circuits to manage data output order across multiple channels.

A multi-port register file architecture uses single-port memory cells with shared decoder logic to manage parallel read operations efficiently.

A bitline precharge voltage generator uses a leakage trimming unit to set the target voltage level.

A semiconductor device adjusts its refresh cycle using a temperature detection circuit and counter logic to reduce power consumption.

A memory module counter tracks host commands to dynamically adjust operating frequency and voltage via stored SPD pairs.

A memory controller inverts MRAM data bits to balance zero and one counts before solder reflow.

A power supplying controller manages pull-down driving voltage for bit line sense amplifiers.

A memory device uses individual power switches for each bank to enable selective deep power down self refresh mode.

Off-module data buffers segment multi-drop topologies into point-to-point links, reducing reflections and increasing end-to-end data rates.

An asymmetric phase-change memory cell switches between three states using a predefined signal level to trigger a physically irreversible third state.

A transmitter uses a self-triggered transition equalizer to drive output nodes during data transitions.

A row hammer preventing circuitry identifies masking entries using address bit comparisons to generate control signals for adjacent row refresh operations.

A DRAM protection method segments memory banks into sub-banks to execute preventive refresh cycles before row activations exceed critical thresholds.

Address capture latches isolate word lines from signal fluctuations to resolve timing instability in high-speed memory arrays.

A memory device uses multiple independent data I/O ports operating at double data rates to transfer values on rising and falling clock edges.

A self-balancing vehicle uses a tiltable platform and spring suspension for hands-free rider control.

A semiconductor command decoder processes address signals across multiple clock cycles to reduce physical pin count.

Segmenting self-refresh operations across staggered bank subsets reduces peak current, lowering physical metal layer requirements and fabrication costs.

A ReRAM program-verify scheme applies opposite polarity pulses to memory elements during programming cycles.

Shaper and timing circuitries drive critical control lines toward asserted voltage levels to enhance read and write operation speeds.

Separately controllable word line and bit line voltage supplies restrict high gate stress to specific memory cells during write operations.