Ferroelectric Memory Bank Cache Control for High-Speed Access
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Solution Overview
Problem
Ferroelectric memory devices face limitations in achieving high-speed operation and reducing capacitor load, as they require large capacitors for non-volatile data storage and are incompatible with SRAM-like access speeds, leading to refresh penalties and limited data rewriting cycles.
Innovation Solution
A ferroelectric memory device with a cache bank and memory bank/cache control sequencer that allows random access without refresh operation delays, using a load capacitor adjustment cell to set up capacitors differently in DRAM and FRAM modes, enabling high-speed operation and reducing polarization inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large BL capacitor is used to maintain non-volatile data storage in FRAM mode, then data retention capability is improved, but access speed deteriorates and cannot achieve SRAM-like operation
Solution Approach 1:
The patent applies dynamics by making the bit line capacitor adjustable rather than fixed. The capacitor value is dynamically changed based on the operational mode: a first capacitor value is used during DRAM mode operation for high-speed access, and a second capacitor value is used during FRAM mode operation for non-volatile data storage. This dynamic adjustment resolves the contradiction between speed and reliability by allowing the system to optimize capacitor size according to the current operational requirements.
2Speed
If the memory operates in DRAM mode with small capacitor for high-speed operation, then access speed is improved, but the ability to hold data during power OFF period deteriorates
Solution Approach 1:
The patent uses dynamics to switch between two operational modes with different capacitor configurations. In DRAM mode, a small first capacitor value enables high-speed operation. In FRAM mode, a larger second capacitor value enables non-volatile data storage during power OFF periods. The system dynamically transitions between these modes based on operational requirements, thus resolving the contradiction between speed and data holding capability.
3Reliability
If refresh operation is executed frequently to maintain data integrity, then data reliability is improved, but data transfer rate deteriorates due to access restrictions during refresh cycles
Solution Approach 1:
The patent applies segmentation by dividing the memory into multiple independent banks. Each bank can be refreshed independently without affecting access to other banks. This allows the memory system to perform refresh operations on one bank while simultaneously allowing external access to other banks, thus maintaining data integrity through frequent refresh while avoiding restrictions on data transfer rate during refresh cycles.
4Adaptability or versatility
If the BL capacitor is fixed to operate in both DRAM and FRAM modes, then operational versatility is improved, but the ability to optimize for high-speed operation deteriorates
Solution Approach 1:
The patent resolves this contradiction by making the capacitor value dynamic rather than fixed. The memory can operate in either DRAM mode or FRAM mode by adjusting the capacitor value to the appropriate setting. This dynamic adjustment allows the system to maintain operational versatility while optimizing performance for the current mode, achieving high-speed operation when in DRAM mode without sacrificing the ability to switch to FRAM mode when non-volatile storage is needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed data restoration at power cutoff and conceals refresh processing, reducing characteristic degradation and achieving SRAM-like access speeds while maintaining non-volatile data storage.
Implementation Method 1
by using the hysteresis characteristic which a ferroelectric capacitor has
Implementation Method 2
executing a DRAM (Dynamic Random Access Memory) mode operation for holding data with quantity of electrical charges charged up
Data Source
AI summary
A ferroelectric memory device includes: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation.