DRAM Row Hammer Protection via Sub-bank Segmentation

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Solution Overview

Problem

Existing DRAM memory technologies face challenges in effectively managing the row hammer effect, particularly in fine-geometry DRAMs where the critical hammer value is low, leading to complex and resource-intensive algorithms that struggle to prevent bit inversions in adjacent rows beyond immediate neighbors.

Innovation Solution

A method that divides the DRAM memory bank into sub-banks and employs a prevention logic to execute a preventive refresh sequence, incrementing activation counters and triggering refreshes before critical hammer values are reached, using a data structure like a tree to manage and prioritize sub-banks needing refreshes, ensuring all rows within a sub-bank are refreshed before they exceed the critical value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a table-based algorithm is used to prevent row hammer effect, then protection against hammer is achieved, but the number of table entries must be 8 times greater for fine-geometry DRAMs with low critical hammer values

Engineering Contradiction:
Improverow hammer protectionVSAvoidtable size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the DRAM bank into multiple sub-banks, each with its own smaller activation counter. This segmentation allows the system to track row activations in finer granularity without requiring a single large table, thus reducing the overall complexity while maintaining protection against row hammer effects in fine-geometry DRAMs

Inventive Principle:
Principle #1Segmentation

2Reliability

If a table-based algorithm with many entries is used, then low critical hammer values are addressed, but the time to go through table entries increases refresh operation time

Engineering Contradiction:
Improverow hammer protectionVSAvoidrefresh operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By segmenting the bank into sub-banks with smaller counters, the patent reduces the time required to monitor and refresh rows. Each sub-counter requires less time to process, allowing the system to address low critical hammer values without excessive refresh delays

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary refresh operations on sub-banks before the critical hammer value is reached. By monitoring activation counts in sub-banks and refreshing proactively, the system prevents row hammer effects without requiring lengthy table traversals during critical moments

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If protection is limited to immediate adjacent rows (scope 1), then the algorithm remains simple, but victim rows beyond immediate neighbors are not protected

Engineering Contradiction:
Improvealgorithm complexityVSAvoidprotection scope
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent uses sub-bank segmentation to extend protection scope. By organizing rows into sub-banks and monitoring activation patterns within each sub-bank, the system can identify and protect victim rows at greater distances from aggressor rows without requiring complex cross-sub-bank coordination logic

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sub-bank structure acts as an intermediary between individual rows. It provides a hierarchical level that enables the system to track and protect rows beyond immediate neighbors while maintaining manageable complexity through the intermediate sub-bank abstraction layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11361811B2Method and circuit for protecting a DRAM memory device from the row hammer effect
Publication Date: 2022.06.14 QUALCOMM TECHNOLOGIES INC
  • US11361811B2 patent drawing
  • US11361811B2 patent drawing
  • US11361811B2 patent drawing

AI summary

A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.