MRAM Data Inversion for Solder Reflow Error Reduction
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Solution Overview
Problem
Non-volatile memories (NVMs), such as MRAMs, face challenges in reliably retaining data at higher temperatures, like those encountered during solder reflow, leading to data loss and requiring costly or complex solutions like larger cell sizes or redundancy.
Innovation Solution
Implementing a stronger error correction code (ECC) with 3-bit correction before solder reflow and selectively inverting data to store more robust states, followed by reverting to 2-bit ECC after reflow, without modifying the NVM bit cells or macro design, to reduce error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stronger ECC (3-bit correction) is applied before solder reflow, then data reliability during reflow is improved, but memory area and complexity increase
Solution Approach 1:
The patent applies dynamic ECC strength adjustment based on operational context. Before solder reflow, the system uses stronger 3-bit correction ECC to ensure data reliability during the high-temperature process. After reflow, the system switches to standard 2-bit correction ECC for normal operation, optimizing the balance between reliability and complexity at different stages of the product lifecycle.
Solution Approach 2:
The patent performs preliminary error correction preparation by applying enhanced ECC (3-bit correction) before the solder reflow process. This preliminary action ensures that data is protected against thermal errors before they occur, without requiring permanent increases in memory complexity or area.
2Reliability
If larger NVM cell size is used, then data retention at high temperature is improved, but performance and power consumption deteriorate
Solution Approach 1:
The patent changes the ECC parameter from standard 2-bit correction to 3-bit correction before solder reflow, providing stronger error protection without altering the physical cell size. This parameter change enables better data retention at high temperatures while maintaining the original cell performance characteristics and avoiding the penalties associated with larger cell sizes.
3Reliability
If redundancy is added to protect against data loss, then reliability is improved, but available memory area decreases
Solution Approach 1:
The patent enhances data protection by changing the ECC correction capability from 2-bit to 3-bit, which provides stronger error protection against data loss during solder reflow. This approach achieves improved reliability without requiring additional redundant memory bits, thereby preserving the full available memory area for actual data storage.
Data Source
AI summary
A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.