DRAM Word Line Activation Counting for Coupling Effect Mitigation
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Solution Overview
Problem
As the degree of integration in memory increases, the coupling effect between word lines in memory devices like DRAM leads to word line disturbance, causing data degradation in adjacent memory cells, especially when frequently activated word lines toggle between activated and deactivated states, and existing schemes for detecting frequently activated word lines may fail due to errors in counting information.
Innovation Solution
A memory core circuit and system that counts and stores the number of activations of word lines, includes a bit line selection unit, a transfer signal generating unit, and a stored value updating unit to manage bit lines and word lines, allowing for the detection of frequently activated word lines and performing special refresh operations to prevent data degradation, with redundancy mechanisms to handle failures in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory is increased, then the memory capacity is improved, but the coupling effect between adjacent word lines increases causing data degradation
Solution Approach 1:
The patent applies preliminary action by performing special refresh operations on memory cells adjacent to frequently activated word lines before data degradation occurs. The system counts word line activations in advance, identifies frequently activated word lines, and proactively refreshes adjacent memory cells to prevent coupling effect damage, rather than waiting for errors to manifest.
Solution Approach 2:
The patent implements feedback by using activation counting circuits that continuously monitor and count the number of times each word line is activated. This count information is fed back to the control logic, which then determines which memory cells require special refresh operations, creating a closed-loop system that adapts to actual usage patterns.
2Reliability
If word line activation counting is implemented to detect frequently activated word lines, then data degradation can be prevented, but errors in counting information may occur
Solution Approach 1:
The patent applies beforehand cushioning by implementing redundancy in the activation counting mechanism. Multiple counting circuits are used to count the same word line activations, and majority voting or error correction logic is employed to detect and correct counting errors before they lead to incorrect refresh decisions, thus cushioning against potential failures.
Solution Approach 2:
The patent uses copying by implementing multiple redundant counting circuits that independently count the same word line activations. The count information is copied across multiple circuits, and the system uses this redundant information to verify correctness and correct errors, ensuring accurate identification of frequently activated word lines.
3Reliability
If special refresh operations are performed on memory cells adjacent to frequently activated word lines, then data degradation is prevented, but additional refresh cycles increase operation time
Solution Approach 1:
The patent applies local quality by performing special refresh operations only on specific memory cells that are adjacent to frequently activated word lines, rather than refreshing the entire memory array. This localized approach targets only the vulnerable cells that need protection, leaving the rest of the memory operating on normal refresh schedules, thus minimizing additional time overhead.
Solution Approach 2:
The patent uses partial action by implementing selective refresh of only those memory cells that require special attention based on activation counting, rather than applying uniform refresh to all cells. This partial approach applies the necessary protective action only where needed, reducing the overall time penalty compared to comprehensive refresh schemes.
Data Source
AI summary
A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines.