Sequenced Memory Component Activation for Peak Power Reduction

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Solution Overview

Problem

Existing memory system activation methods consume high peak power, generate excessive heat, and occupy significant space, as they activate all memory components simultaneously, which is inefficient and costly, especially in mobile devices.

Innovation Solution

Implementing a sequenced activation of memory components, where some but not all memory components are activated at the same time, using a designated activation sequence to reduce peak power consumption and allow for smaller voltage regulators, thereby enhancing efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all memory components are activated simultaneously, then the memory system becomes operational quickly, but peak power consumption increases and heat generation becomes excessive

Engineering Contradiction:
Improvememory system activation speedVSAvoidpeak power consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the memory components into multiple groups or banks that are activated in sequential stages rather than all at once. This segmentation allows the system to spread out the power consumption over time, reducing peak power requirements while still achieving relatively fast overall activation by parallel activating multiple groups in succession

Inventive Principle:
Principle #1Segmentation

2Productivity

If all memory components are activated simultaneously, then the memory system is fully operational, but heat generation becomes excessive and space requirements increase

Engineering Contradiction:
Improvememory system operational capacityVSAvoidheat generation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The memory system is divided into multiple activatable groups, allowing the system to achieve full operational capacity through sequential activation rather than simultaneous activation. This segmentation reduces heat generation by spreading the thermal load over time and allows for better thermal management in the device

Inventive Principle:
Principle #1Segmentation

3Productivity

If all memory components are activated simultaneously, then the system is ready for use, but voltage regulators must be large and costly

Engineering Contradiction:
Improvesystem readinessVSAvoidvoltage regulator size and cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By segmenting the memory activation into multiple groups, the patent reduces the peak current demand that voltage regulators must handle. This allows for the use of smaller, less expensive voltage regulators that can be activated in sequence rather than requiring large regulators capable of handling the sum of all memory component activation currents simultaneously

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs periodic or staged activation of memory groups, where each group is activated in successive time periods. This periodic action allows voltage regulators to operate at lower power levels during each stage, reducing the size and cost requirements compared to simultaneous activation of all components

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240412770A1Sequenced activation of memory components
Publication Date: 2024.12.12 MICRON TECHNOLOGY INC
  • US20240412770A1 patent drawing
  • US20240412770A1 patent drawing
  • US20240412770A1 patent drawing

AI summary

A method includes providing, in accordance with a memory component activation sequence, a first activation power to a first memory component of a plurality of memory components for a first time period, where the first activation power is provided in the absence of providing an activation power to at least one other memory component of the plurality of memory components during the first time period. The method includes providing, in accordance with the memory component activation sequence, a second activation power to a second memory component for a second time period.