Memory Device Double Data Rate I/O Ports
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Solution Overview
Problem
Current memory devices face limitations in achieving high random transaction rates due to constraints in data access and processing capabilities, particularly in handling concurrent and randomized operations across multiple storage locations.
Innovation Solution
The implementation of multiple independent data I/O ports operating at double data rates, allowing simultaneous read and write transactions on both rising and falling edges of a clock, along with pipelined bank operations and address latching at double data rates, enables efficient and randomized access to storage locations within a memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple independent data I/O ports operate at double data rates with pipelined bank operations, then random transaction rate is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent banks (first bank, second bank, etc.) that can operate simultaneously. Each bank has its own address latching and data I/O capabilities, allowing parallel processing of random transactions. This segmentation enables high random transaction rates by distributing the transaction load across multiple independent operational units.
Solution Approach 2:
The patent implements double data rate (DDR) operation by utilizing both rising and falling edges of the clock signal as separate timing dimensions. Address values are latched on one edge (e.g., rising edge) while data transactions occur on the opposite edge (e.g., falling edge), effectively doubling the transaction rate without proportionally increasing circuit complexity.
2Speed
If address values are latched at double data rates on both rising and falling edges, then data access speed is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The system uses periodic clock signals with distinct rising and falling edges to latch address values and initiate transactions. By alternating operations between these periodic edges, the system achieves double data rate performance while maintaining manageable timing requirements for manufacturing.
Solution Approach 2:
Address values are latched in advance on one clock edge before the actual data transaction occurs on the subsequent edge. This preliminary latching action separates the address decoding function from the data transfer function, allowing each to be optimized independently and reducing the precision requirements for simultaneous operations.
3Productivity
If concurrent read and write transactions are performed simultaneously, then productivity is improved, but reliability may worsen due to potential conflicts
Solution Approach 1:
Multiple independent banks allow read and write transactions to be segregated into different operational units. When a read transaction is directed to bank 0 and a write transaction to bank 1, they execute simultaneously without interfering with each other, maintaining both high productivity and transaction reliability.
Solution Approach 2:
The control logic acts as an intermediary that receives transaction requests, determines the appropriate bank assignments, and coordinates the timing of concurrent operations. This mediation ensures that simultaneous read and write transactions are properly managed, preventing conflicts while maximizing throughput.
Data Source
AI summary
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.