CMOS Nonvolatile Memory Cell With Parallel Capacitor for Fast Read
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Solution Overview
Problem
Current non-volatile memory technologies, such as Flash memory, face challenges with slow read times due to high threshold voltage requirements and the need for simultaneous activation and reading, which complicates multilevel storage and device optimization.
Innovation Solution
The integration of a CMOS-compatible non-volatile storage element with a parallel storage capacitor allows for fast read times comparable to DRAM, enabling decoupling of activation and access operations, and utilizing 'drain-side' erasing to avoid disturbances in neighboring cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Flash memory uses heavily doped transistor regions to engineer the floating-gate transistor for write and erase operations, then write and erase functions are achieved, but the threshold voltage becomes relatively high (approximately 1V), resulting in slow read times
Solution Approach 1:
The patent segments the memory cell into distinct functional components: a first transistor optimized for write/erase operations with heavily doped regions and high threshold voltage, and a second transistor optimized for read operations with lightly doped regions and low threshold voltage. This segmentation allows each transistor to be independently optimized for its specific function, resolving the contradiction between write/erase capability and read speed.
Solution Approach 2:
The patent applies local quality by creating different doping profiles in different regions of the memory cell. The first transistor has heavily doped source and drain regions to achieve high threshold voltage for write/erase operations, while the second transistor has lightly doped regions to achieve low threshold voltage for fast read operations. This localized optimization of material properties resolves the contradiction between manufacturing write/erase functions and achieving fast read times.
2Reliability
If Flash memory activates and reads simultaneously to provide reprogrammable non-volatile memory, then non-volatility is achieved, but read times become slower compared to DRAM
Solution Approach 1:
The patent employs preliminary action by using the first transistor to pre-charge or pre-discharge the storage node before the actual read operation. The storage node is prepared in advance by the first transistor based on the stored data state, so that when the second transistor is activated for reading, the bit line already contains the correct voltage level. This preliminary preparation eliminates the need for simultaneous activation and reading, achieving both non-volatility and fast read times.
Solution Approach 2:
The storage node acts as an intermediary between the first transistor (optimized for write/erase) and the second transistor (optimized for read). The first transistor modifies the charge state of the storage node, which then serves as the input condition for the second transistor's read operation. This intermediary mechanism allows the two transistors to operate at different times with different optimization goals, resolving the contradiction between non-volatility and read speed.
3Reliability
If Flash memory uses high threshold voltage transistors to avoid unintended disturbances in unselected cells, then cell isolation is achieved, but the current from source to drain is relatively low, requiring longer sensing time
Solution Approach 1:
The patent segments the sensing function between two transistors: the first transistor with high threshold voltage provides cell isolation and prevents unintended disturbances in unselected cells, while the second transistor with low threshold voltage provides high current drive capability for fast sensing. This segmentation allows both cell isolation and fast sensing to be achieved simultaneously by assigning different functions to different components.
Solution Approach 2:
The memory cell structure achieves multi-functionality by incorporating two transistors with complementary characteristics. The first transistor specializes in write/erase and cell isolation functions, while the second transistor specializes in fast read operations. Together, they create a universal memory cell that can perform all required functions with optimal performance in each mode, resolving the contradiction between cell isolation and sensing speed.
Data Source
AI summary
Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element.