Row Hammer Prevention Circuitry for DRAM Access Pattern Monitoring
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Solution Overview
Problem
Volatile memory devices like DRAM experience bit-flip and row hammer phenomena due to adverse voltage distribution between word lines, leading to data loss and corruption, which existing technologies fail to effectively prevent.
Innovation Solution
A memory device with row hammer preventing circuitry that includes a first table for storing hit counts and address bits, a second table for safe bits and a counter, and logic to identify masking entries for additional refresh operations based on hit counts and bit comparisons, thereby generating control signals for adjacent row refresh.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If intensive access to one word line is performed, then access speed is improved, but row hammer phenomenon occurs causing bit-flip or data loss
Solution Approach 1:
The patent performs preliminary detection of row hammer vulnerability by monitoring access patterns and identifying frequently accessed rows before actual row hammer damage occurs. The system proactively identifies target rows that are likely to cause bit-flip in adjacent rows and preemptively applies refresh operations to protect adjacent memory cells, preventing data loss before it happens.
Solution Approach 2:
The patent applies preliminary anti-action by detecting rows that are intensively accessed and likely to cause row hammer effects, then selectively applying refresh operations to adjacent rows before damage occurs. The row hammer preventing circuitry generates control signals to refresh adjacent rows in advance, counteracting the potential harmful effects of intensive access patterns before they can corrupt data.
2Reliability
If additional refresh operations are performed on adjacent rows, then row hammer prevention is improved, but memory access latency increases
Solution Approach 1:
The patent applies local quality by selectively applying refresh operations only to specific adjacent rows that are vulnerable to row hammer effects, rather than performing blanket refresh operations on all memory rows. The system identifies target rows through address bit comparison and monitoring circuits, then applies refresh control signals only to the necessary adjacent rows, minimizing unnecessary refresh operations and reducing overall latency.
Solution Approach 2:
The patent uses partial action by performing refresh operations only on the minimal necessary adjacent rows that are at risk, rather than refreshing all rows. The row hammer preventing circuitry determines which adjacent rows need protection based on the identified target row, and applies refresh operations only to those specific rows, avoiding excessive refresh operations that would increase latency unnecessarily.
3Measurement precision
If comprehensive monitoring of all rows is performed, then detection accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent extracts only the necessary information for row hammer detection by focusing on specific address bits (such as the most significant bit) rather than monitoring all address bits for all rows. The extraction circuit identifies target rows by comparing specific address bit patterns, and the monitoring circuitry only tracks access patterns for rows that match the target pattern, reducing the overall complexity of the detection system while maintaining effective coverage.
Solution Approach 2:
The patent segments the monitoring function by dividing the memory address space into segments based on address bit patterns. Instead of uniformly monitoring all rows, the system identifies and monitors only those rows that match specific address bit criteria (target rows), and applies refresh operations only to their adjacent rows. This segmentation approach reduces the complexity of comprehensive monitoring while maintaining detection accuracy for vulnerable rows.
Data Source
AI summary
A row hammer preventing circuitry including: a first table storing a count value representing a hit count and an address bit of multiple entries, each entry corresponding to access-requested target rows; a second table including safe bits and a safe bit counter; and a row hammer preventing logic to identify masking entries, on which a masking comparison is to be performed, among the entries on the basis of the safe bit counter, to determine a hit or miss on the basis of whether other bits except an MSB among address bits of an access-requested target row match other bits except an MSB among address bits of the masking entries, and to generate a control signal indicating an additional refresh on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a threshold value.