Phase Change Memory Data Drift Prevention via Selective Refresh
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Solution Overview
Problem
Phase changeable memory devices experience data drift over time, leading to mismatches in read and write information, making it difficult to restore stored data and causing system malfunctions.
Innovation Solution
A semiconductor system with a phase changeable memory device and a controller that includes a cross-point array with phase changeable memory cells and a controlling unit, which regularly and irregularly refreshes the memory cells using refresh commands and signals to prevent data drift, ensuring accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If phase changeable memory cells are used for non-volatile storage, then data retention capability is improved, but data drift occurs over time causing read/write mismatch
Solution Approach 1:
The patent implements regular refresh operations at predetermined time intervals to periodically restore the resistance values of phase changeable memory cells. This periodic action prevents data drift by continuously maintaining the memory cells in their correct resistance states, thereby ensuring long-term data retention without read/write mismatch.
Solution Approach 2:
The patent performs preliminary refresh operations on phase changeable memory cells before read/write operations are executed. By proactively restoring resistance values in advance, the system prevents potential data drift from causing read/write mismatches, ensuring data reliability before actual data access occurs.
2Reliability
If regular refresh operations are performed on all memory cells, then data drift is prevented, but power consumption increases
Solution Approach 1:
The patent implements selective refresh operations that target only specific memory cells or regions exhibiting signs of data drift or located in high-risk areas, rather than refreshing all memory cells uniformly. This localized approach maintains data integrity in critical areas while minimizing unnecessary power consumption in stable regions.
Solution Approach 2:
The patent performs refresh operations on a partial basis, focusing on memory cells that require refreshing based on usage patterns, time since last access, or detected drift indicators. This partial action approach prevents full-refresh power consumption while still maintaining data integrity for the most critical memory cells.
3Use of energy by moving object
If selective refresh operations are implemented, then power consumption is reduced, but data drift may occur in unrefreshed memory cells
Solution Approach 1:
The patent implements monitoring mechanisms that detect data drift conditions in memory cells and trigger refresh operations in response. This feedback-based approach ensures that refresh operations are activated only when necessary, maintaining data integrity while minimizing power consumption by avoiding unnecessary refresh operations in stable memory cells.
Solution Approach 2:
The patent enables memory cells to effectively monitor their own state and trigger refresh operations when drift is detected, or allows the system to identify and refresh only the specific cells that need it based on their individual characteristics and usage patterns. This self-service approach optimizes the balance between data integrity and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The regular and irregular refresh operations effectively prevent data drift, maintaining data integrity and system stability by equalizing the resistance of memory cells and reducing power consumption during refresh operations.
Implementation Method 1
the phase changeable memory cell may include a phase changeable material
Data Source
AI summary
A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.