MRAM Read Circuit Calibration for Sensing Margin

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Solution Overview

Problem

MRAM devices have limited sensing margin due to the narrow resistance ratio of their high-to-low resistance states, which affects the accuracy of resistance state determination, especially at elevated temperatures.

Innovation Solution

A nonvolatile memory device with a read circuit that includes variable target resistors, a sense amplifier, and a multiplexer, allowing for calibration to set the reference resistance between the low and high resistance distributions, thereby improving the sensing margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional read circuit with fixed resistors is used, then the circuit structure is simple, but the sensing margin is limited due to the narrow resistance ratio of MRAM high-to-low resistance states

Engineering Contradiction:
Improvesensing marginVSAvoidread circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by replacing fixed resistors with variable resistors (first and second variable resistors) in the read circuit. These variable resistors can be adjusted during calibration to optimize the sensing margin for different MRAM resistance distributions, transforming a static circuit into an adaptive one that responds to varying operational conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by introducing adjustable resistance values through the variable resistors. The resistance parameters of the first and second variable resistors can be modified during calibration to match the specific high and low resistance distributions of the MRAM cells, thereby optimizing the sensing margin for accurate state detection.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the reference resistance is not calibrated, then the read circuit operation is simple, but the accuracy of resistance state determination deteriorates at elevated temperatures

Engineering Contradiction:
Improveresistance state determination accuracyVSAvoidcalibration process
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing calibration of the variable resistors before normal read operations. During this preliminary phase, the first and second variable resistors are adjusted to establish optimal reference resistance values that account for temperature variations and manufacturing tolerances, ensuring high measurement precision during subsequent operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the calibration process where the resistance states of MRAM cells are measured and used to adjust the variable resistors. This feedback loop allows the system to optimize its reference resistance values based on actual device characteristics, improving the accuracy of resistance state determination.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If fixed resistance values are used in the read circuit, then the manufacturing process is simpler, but the adaptability to different resistance distributions is reduced

Engineering Contradiction:
Improveadaptation to resistance distributionsVSAvoidread circuit fabrication
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent applies dynamics by incorporating variable resistors that can be adjusted after manufacturing to adapt to different MRAM resistance distributions. This dynamic capability allows the same circuit design to work with varying high and low resistance values across different manufacturing batches or temperature conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes through the use of adjustable resistance values in the first and second variable resistors. These parameters can be tuned during calibration to match specific resistance distributions, providing adaptability without requiring different fixed resistor values for each manufacturing variation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the sensing margin of MRAM devices by accurately distinguishing between low and high resistance states, even at elevated temperatures, through the calibration of the read circuit's resistance settings.

Implementation Method 1

When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ. Conversely, the electrical resistance of the MTJ is high when the magnetization directions of the magnetic free and reference layers are substantially anti-parallel or oriented in opposite directions.

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 2

electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer

Methodology Applied
Scientific EffectElectron tunneling:

Data Source

PatentUS11854591B2Magnetic memory read circuit and calibration method therefor
Publication Date: 2023.12.26 AVALANCHE TECHNOLOGY INC
  • US11854591B2 patent drawing
  • US11854591B2 patent drawing
  • US11854591B2 patent drawing

AI summary

The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.