SRAM Bit Line Driver Reducing Voltage Swing for Power
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Solution Overview
Problem
SRAM arrays consume significant power due to the discharge and charging operations of bit lines, primarily during read and write cycles, which is inefficient and increases energy consumption.
Innovation Solution
The SRAM array is configured to charge bit lines to a voltage less than the supply voltage by reducing the voltage swing, utilizing a bit line driver with a write circuit and pre-charge circuit that supply voltage less than the supply voltage by the threshold voltage of a transistor, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit lines are charged to the supply voltage during read and write cycles, then the memory operation reliability is improved, but the power consumption increases significantly
Solution Approach 1:
The patent changes the voltage parameter from full supply voltage to a reduced voltage level. Specifically, bit lines are charged to a voltage less than the supply voltage by the threshold voltage of the access transistor, reducing the voltage swing while maintaining sufficient logic levels for reliable operation. This parameter change directly reduces power consumption proportional to the square of the voltage reduction.
2Use of energy by moving object
If the voltage swing of bit lines is reduced to lower power consumption, then energy efficiency is improved, but the voltage may become insufficient for reliable logic state representation
Solution Approach 1:
The access transistor serves as an intermediary element that naturally limits the voltage swing on bit lines. By utilizing the transistor's threshold voltage characteristic, the circuit automatically charges bit lines to an appropriate voltage level that is sufficient for logic representation while inherently reducing the voltage swing to save power, without requiring additional control circuitry.
Data Source
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AI summary
A bit line driver for a static random access memory (SRAM) cell including; a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.