Semiconductor Memory Strobe Signal Pulse Width Control

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Solution Overview

Problem

The existing semiconductor memory devices face challenges in maintaining sufficient operation margins and accuracy due to the short pulse width of the main strobe signal, which is exacerbated by the high speed of external clock cycles, leading to potential operation errors and deteriorated circuit characteristics.

Innovation Solution

A semiconductor memory device with a reference strobe signal generator and a main strobe signal generator that extends the pulse width of the main strobe signal in a bank grouping mode, ensuring sufficient operation margins and preventing errors by controlling the pulse width based on bank grouping signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the external clock cycle is shortened to increase operating speed, then productivity is improved, but the pulse width of the main strobe signal becomes too short causing operation errors and deteriorated circuit characteristics

Engineering Contradiction:
Improveoperating speedVSAvoidoperation accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic pulse width control where the main strobe signal generator adjusts the pulse width of the main strobe signal based on the bank grouping mode. In normal mode, the pulse width corresponds to one external clock cycle (1tCK), but in bank grouping mode, it is extended to a reference pulse width (e.g., 1.5tCK or 2tCK). This dynamic adjustment allows the system to maintain reliability during continuous column accesses in grouped banks while supporting high-speed operation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the pulse width of the main strobe signal is reduced to match the external clock cycle, then productivity is improved, but the operation margin for column selection and data application becomes insufficient

Engineering Contradiction:
Improveclock cycle speedVSAvoidoperation margin
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the time parameter (pulse width) of the main strobe signal based on the operating mode. By switching between normal mode (1tCK) and bank grouping mode (extended pulse width), the system optimizes the balance between speed and operation margin. The main strobe signal generator responds to bank grouping signals to extend the pulse width when needed, ensuring sufficient time for column selection and data application without sacrificing overall productivity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the main strobe signal has a very small pulse width, then productivity is improved, but the signal cannot make full swing to destination causing deteriorated circuit characteristics

Engineering Contradiction:
Improvesignal cycle speedVSAvoidsignal swing capability
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The system dynamically adjusts the main strobe signal pulse width to ensure adequate signal swing capability. When bank grouping mode is detected, the extended pulse width provides sufficient time for the signal to propagate and establish proper voltage levels at the destination, preventing signal degradation while maintaining high-speed operation capability in normal modes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7885127B2Semiconductor memory device and operation method thereof
Publication Date: 2011.02.08 MIMIRIP LLC
  • US7885127B2 patent drawing
  • US7885127B2 patent drawing
  • US7885127B2 patent drawing

AI summary

A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks.