Resistive Memory Read Circuit Sneak Current Compensation
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Solution Overview
Problem
Sneak currents in resistive memory devices reduce the read margin and cause delays in read operations, as they alter the current path and make it difficult to accurately sense the resistance state of memory cells.
Innovation Solution
The implementation of a semiconductor memory unit with a read circuit that generates a bias current by combining a reference current and a compensation current, where the bias information is determined and stored before the read operation to maximize the read margin, compensating for sneak currents and optimizing the read voltage and current levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read operation is performed in resistive memory devices, then the read operation is simple and fast, but the read margin is reduced due to sneak currents
Solution Approach 1:
The read circuit is segmented into multiple functional units: a first current generating unit for generating reference current, a second current generating unit for generating compensation current based on stored bias information, a sensing unit for sensing data, and a read voltage driving unit for applying read voltage. This segmentation allows each unit to perform a specific function, improving read margin through compensation while maintaining organized complexity.
Solution Approach 2:
Bias information indicating the optimal bias current amount for maximum read margin is determined through calibration and stored in the read circuit before normal read operations. During read operations, the second current generating unit retrieves this pre-stored bias information and generates the appropriate compensation current, eliminating the need for real-time calibration and maintaining fast read speeds.
2Reliability
If bias current compensation is implemented during read operation, then read margin is increased, but read speed is delayed due to real-time calculation
Solution Approach 1:
The optimal bias current amount is determined through calibration operations performed beforehand, and this bias information is stored in the read circuit. During normal read operations, the stored bias information is directly retrieved and used to generate compensation current, avoiding real-time calculation delays while maintaining maximum read margin.
Solution Approach 2:
Instead of performing complex real-time calculations during read operations, the system creates a simplified copy of the optimal compensation parameters through pre-calibration. The stored bias information serves as a lookup table that provides pre-computed compensation values, allowing fast retrieval without sacrificing read margin optimization.
3Measurement precision
If sneak current compensation is not performed, then read operation is fast and simple, but measurement precision of resistance state is reduced
Solution Approach 1:
The read circuit is divided into specialized units: a first current generating unit for reference current, a second current generating unit for compensation current based on stored bias information, a sensing unit for accurate data sensing, and a read voltage driving unit. This segmentation enables precise compensation for sneak currents while maintaining an organized and manageable circuit structure.
Solution Approach 2:
Bias information serves as an intermediary element that bridges the calibration process and normal read operations. The stored bias information contains pre-determined optimal compensation parameters that mediate between the complex physics of sneak currents and the simplified operation of normal read cycles, enabling accurate sensing without real-time complexity.
Data Source
AI summary
An electronic device includes a semiconductor memory unit. The semiconductor memory unit may include a cell array suitable for including a plurality of resistive memory cells which are arranged in a plurality of column lines and a plurality of rows lines, and a read circuit. The read circuit is suitable for, in a read operation, generating a bias current based on bias information, supplying the bias current to a sensing node, supplying a read current from the sensing node to a column line selected from among the plurality of column lines, and sensing data stored in a selected memory cell coupled to the selected column line using a voltage level at the sensing node. The bias information is determined and stored in the semiconductor memory unit before the read operation starts.