Dual Data-Dependent Busses for Memory Array Voltage Scaling
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Solution Overview
Problem
In three-dimensional semiconductor memory arrays, the high voltages required for programming and erasing passive element memory cells pose a challenge as they do not scale well with decreasing word line and bit line pitches, leading to compatibility issues with smaller array line pitches and increased leakage current in unselected memory cells.
Innovation Solution
The implementation of dual data-dependent busses for coupling read/write circuits to a memory array, allowing for reduced voltage requirements by using a data-dependent first bus for one mode and a second data-dependent bus for another mode, thereby relaxing the voltage demands on word line and bit line decoder circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high voltage is used for programming and erasing memory cells, then programming and erasing operations can be achieved, but the voltage requirements do not scale well with decreasing word line and bit line pitches
Solution Approach 1:
The patent segments the bit line into two separate busses: a first data bus for coupling to memory cells in a first set of columns and a second data bus for coupling to memory cells in a second set of columns. This segmentation allows independent voltage control and reduces the voltage requirements on individual decoder circuits, enabling scaling to smaller pitches.
Solution Approach 2:
The patent introduces data-dependent switching circuitry as an intermediary between the decoder circuits and the memory cells. This switching mechanism selectively connects bit line decoder output nodes to appropriate memory cells based on data values, allowing reduced voltage operation while maintaining full programming and erasing functionality.
2Reliability
If high voltage is applied to memory cells, then programming operations are enabled, but leakage current increases in unselected memory cells
Solution Approach 1:
The patent applies different voltage conditions to different spatial regions of the memory array by using separate first and second data busses for different column sets. Unselected memory cells can be maintained at lower voltages or put into high-impedance states, reducing leakage current while selected cells receive the necessary high voltage for programming operations.
Solution Approach 2:
The patent employs data-dependent dynamic switching that adjusts the connection state between decoder outputs and memory cells based on the data being written. This dynamic control allows precise voltage application only to selected cells, minimizing leakage in unselected cells while maintaining reliable programming operation.
Data Source
AI summary
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.