RRAM Sense Module Dynamic Voltage Control
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Solution Overview
Problem
Current RRAM technologies face read disturbance issues due to high bit line voltage levels during read operations, which can alter the resistance value of memory cells and lead to failed read operations, while keeping the voltage low extends read access time.
Innovation Solution
The RRAM circuit and read method incorporate a sense module with a switch and pull-up devices to generate and compare data and reference voltages, controlling the bit line voltage and preventing it from exceeding a certain level, thereby reducing read disturbance without prolonging access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line voltage level is kept low to reduce read disturbance, then the RRAM memory cell resistance value remains stable, but the read access time is extended
Solution Approach 1:
The patent employs dynamic voltage control by switching between different voltage levels during the read operation. A first voltage level is applied initially to enable reading, then a second (lower) voltage level is applied to prevent read disturbance. This dynamic adjustment allows the system to achieve both fast read access and low read disturbance, resolving the contradiction between read speed and read reliability.
Solution Approach 2:
The read operation is divided into distinct time periods: a first time period where a higher voltage is applied for rapid data retrieval, and a second time period where a lower voltage is applied to maintain stability. This periodic voltage adjustment enables the system to balance between read access speed and read disturbance prevention.
2Productivity
If the bit line voltage level is increased to reduce read access time, then the read operation speed increases, but the RRAM memory cell resistance value changes causing read failure
Solution Approach 1:
The system dynamically adjusts the bit line voltage level based on the timing of the read operation. During the initial phase, a higher voltage is applied to ensure fast read access. Subsequently, the voltage is reduced to a lower level to prevent resistance changes in the memory cell. This dynamic voltage control enables both high read speed and high read success rate.
Solution Approach 2:
The patent applies a higher voltage level in the first time period as a preliminary action to quickly retrieve data before the memory cell resistance can be significantly affected. This preliminary high-voltage pulse enables fast read access, followed by a transition to lower voltage to maintain reliability.
Data Source
AI summary
An RRAM circuit includes word lines, bit lines, source lines, memory cells, and a sense module. Each of the memory cells includes a resistor and a transistor. The resistor alternates between a high impedance and a low impedance, and is coupled to one of the bit lines. The transistor is controlled by one of the word lines and coupled between the resistor and one of the source lines. The sense module includes a switch and a sense amplifier. The switch is controlled by an output signal and coupled to one of the bit lines. The sense amplifier compares the data voltage, which is generated by a current flowing through the switch and the resistor, and a reference voltage to generate the output signal. The switch is turned off when the data voltage exceeds the reference voltage, and is turned on otherwise.