Scan Flip Flop State Retention for Standby Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for retaining the state of an integrated circuit during standby mode require complex power supply routing and significant area overhead, making them difficult to implement effectively.
Innovation Solution
A system using M scan flip flops divided into groups, with a merged scan flip flop configuration that allows state data to be temporarily held and serialized for storage in a memory unit, utilizing a single power supply and reducing the need for additional power routing lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If balloon flip flops with shadow latches are used to retain state data, then state retention during standby mode is achieved, but device complexity and area increase significantly
Solution Approach 1:
The patent merges the scan flip flop and shadow latch into a single integrated structure. The scan flip flop itself is configured to retain state data during standby mode by preventing data output to subsequent flip flops while maintaining internal state, eliminating the need for separate shadow latch structures and their associated power supply routing.
Solution Approach 2:
The scan flip flop is designed to perform multiple functions: normal data storage during active mode and state retention during standby mode. By controlling the output enable signal, the same flip flop structure serves both operational modes without requiring separate dedicated retention structures.
2Reliability
If balloon flip flops with shadow latches are used to retain state data, then state retention during standby mode is achieved, but chip area increases significantly
Solution Approach 1:
The patent merges the scan flip flop and shadow latch into a single integrated structure. The scan flip flop itself is configured to retain state data during standby mode by preventing data output to subsequent flip flops while maintaining internal state, eliminating the need for separate shadow latch structures and their associated power supply routing.
Solution Approach 2:
The patent extracts the redundant shadow latch structure from the design and eliminates it entirely. By using the scan flip flop's inherent capability to hold state data through controlled output disabling, the separate shadow latch component is removed, reducing chip area.
3Reliability
If integrated circuit remains powered during standby mode, then state data is maintained, but power consumption increases
Solution Approach 1:
The patent performs preliminary action by disabling the output enable signal before entering standby mode. This prevents the flip flop from driving output signals during standby, thereby eliminating dynamic power consumption associated with output switching while maintaining the internal state data intact.
Solution Approach 2:
The patent uses periodic clocking during active mode to update state data, then transitions to a non-clocking standby mode where state data is held static. This periodic active/static pattern reduces average power consumption while maintaining state retention capability.
Data Source
AI summary
According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.