Multi-Port Register File Using Single-Port Cells and Shared Decoders
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Solution Overview
Problem
Conventional multi-port register files face challenges such as increased cell area and wire pitch with the number of read ports, complex wiring, and increased access times due to the need for multiple decoder elements and complex bit cell layouts, leading to crosstalk and inefficiencies.
Innovation Solution
A register file architecture utilizing single port memory bit cells with multiple read ports, where each bit cell has a single write port and a single read port, and employing n decoder devices, clock control buffers, and selector devices to manage read operations in parallel, reducing the complexity and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional multi-port register files use multiple decoder elements and complex bit cell layouts to provide multiple read ports, then the number of read ports is increased, but the cell area and wire pitch increase
Solution Approach 1:
The patent divides the register file into multiple banks, where each bank contains multiple bit cells that can be independently accessed. This segmentation allows multiple read ports to share access to the same physical memory cells through bank switching, reducing the need for separate decoder elements for each port and thereby reducing cell area and wire pitch.
Solution Approach 2:
The patent implements a universal decoder structure that serves multiple read ports simultaneously. Instead of having dedicated decoder elements for each read port, a single decoder can service multiple ports by time-multiplexing or space-multiplexing through the bank structure, reducing the overall number of decoder elements and associated wiring.
2Adaptability or versatility
If conventional multi-port register files use multiple decoder elements and complex bit cell layouts to provide multiple read ports, then the number of read ports is increased, but the wiring complexity increases
Solution Approach 1:
By segmenting the register file into banks with shared decoders, the patent reduces the number of independent wiring paths needed. Each bank can be accessed through a common decoder infrastructure, eliminating the need for separate complex wiring for each read port and simplifying the overall interconnect structure.
Solution Approach 2:
The patent merges the decoder functionality across multiple read ports by implementing shared decoder elements that service multiple ports. This consolidation reduces the total number of decoder units and their associated wiring, thereby reducing overall wiring complexity while maintaining multi-port functionality.
3Adaptability or versatility
If conventional multi-port register files use multiple decoder elements and complex bit cell layouts to provide multiple read ports, then the number of read ports is increased, but the access time increases
Solution Approach 1:
The bank-based segmentation allows parallel access to multiple banks simultaneously through different read ports. Since each bank can be independently accessed and the decoders are shared rather than sequential, multiple read operations can proceed in parallel, reducing overall access time compared to sequential decoding approaches.
Solution Approach 2:
The patent implements pre-charging of bit lines and early decoding stages that prepare the read path in advance. By pre-charging bit lines before the actual read operation and using efficient bank selection logic, the access time is reduced while maintaining the ability to service multiple read ports.
Data Source
AI summary
An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single bit cell write port and a single read port connecting a respective local bit line, wherein corresponding parallel activated single bit cells output a stored data value in parallel at n read port outputs to a respective local bit line of n local bit lines, each single bit cell accessed in parallel according to a decoded read address signal. A receiver device is provided implementing n selection logic devices corresponding to n read ports, each selection logic device receiving each the n local bit line output values from the n single bit cells, and implementing logic based directly on the decoded read address signal to select a respective local bit line output as a global output bit.