Memory Array Gate Drive Voltage Boost Schemes
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Solution Overview
Problem
Magnetic memory technologies like Phase Change RAM and Spin Moment Transfer MRAM require high programming currents, which cause significant stress on cell transistors when high voltages are applied between the gate and source/drain, leading to reduced transistor life.
Innovation Solution
A circuit with separately controllable word line and bit line voltage supplies is used to apply high gate to drain or source voltage only to cells being written, minimizing stress on cell transistors not involved in the writing process by restricting the high voltage to specific rows and columns of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high gate to source/drain voltage is applied to program magnetic memory cells, then sufficient programming current is achieved, but transistor life is significantly reduced
Solution Approach 1:
The bit line is divided into multiple segments, with each segment serving a specific row of memory cells. By activating only the required bit line segment during programming operations, the patent limits high voltage stress to only the necessary transistor subsets, thereby preserving overall transistor reliability while achieving sufficient programming current where needed
Solution Approach 2:
The patent implements separate voltage supplies for different bit line segments, allowing localized application of high gate to source/drain voltage only to the specific row and column being programmed. This localized voltage application ensures sufficient programming current for the targeted cell while minimizing voltage stress on transistors in other rows and columns, thus resolving the contradiction between programming effectiveness and transistor longevity
2Ease of operation
If high voltage is applied to all cells in a row, then programming is simplified, but unnecessary stress is applied to cells not being written
Solution Approach 1:
The bit line is segmented into multiple independent sections, each controllable by its own voltage supply. This segmentation enables selective activation of only the specific bit line segment corresponding to the target row during programming operations, thereby simplifying the programming operation for targeted cells while preventing voltage stress from being applied to cells in other rows that are not being written
Solution Approach 2:
By providing separate voltage supplies for each bit line segment, the patent enables localized control of high voltage application. During programming, high gate to source/drain voltage is applied only to the specific bit line segment and column intersection corresponding to the target cell, ensuring ease of operation for the intended programming task while avoiding harmful voltage stress on non-target cells through precise spatial localization of the voltage application
Data Source
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AI summary
This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array During the write operation the voltage is raised for the word line of only one row of the array The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row