Embedded Memory Redundancy for Low-Voltage Operation
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Solution Overview
Problem
Integrated circuits face increased failures and unreliable operation when power supply voltage is lowered, particularly due to device mismatches and transistor size reduction, which is exacerbated by the need for large speed/reliability guard bands in embedded memories.
Innovation Solution
Incorporating test circuits and redundant memory cells to identify and substitute for weakest cells, allowing for reliable operation at lower power supply voltages by determining the minimum operating voltage through multiplexer and comparator-based testing, and using control registers to manage power supply voltage adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is lowered to reduce power consumption, then energy efficiency is improved, but reliability deteriorates due to increased failures in memory cells
Solution Approach 1:
The patent performs preliminary identification of weakest memory cells through testing at different voltage levels before actual low-voltage operation. By pre-characterizing cell weaknesses and establishing replacement mappings, the system ensures reliable operation at lower voltages without encountering failures during normal operation.
Solution Approach 2:
The patent changes the operating voltage parameter dynamically, testing memory cells at multiple voltage levels to identify the minimum operating voltage for each cell. Weakest cells are identified by their higher minimum operating voltage requirements, and the system adjusts voltage assignments to operate cells above their threshold, enabling lower overall power consumption while maintaining reliability.
2Productivity
If transistor size is decreased to improve integration density, then productivity is improved, but manufacturing precision deteriorates due to increased device mismatches
Solution Approach 1:
The patent applies local quality by individually characterizing each memory cell's performance characteristics rather than treating all cells uniformly. Each cell is tested to determine its specific minimum operating voltage and weakest cell status, allowing tailored voltage assignments and replacements based on local cell properties rather than global averages.
Solution Approach 2:
The patent implements feedback through a testing mechanism that measures actual memory cell performance and uses this information to identify weakest cells and determine appropriate replacement strategies. The system continuously monitors and adjusts based on measured cell characteristics, compensating for manufacturing variations through data-driven decision making.
3Reliability
If speed/reliability guard band margin is increased to cover device mismatches, then reliability is improved, but power consumption increases due to higher operating voltage requirements
Solution Approach 1:
The patent performs preliminary testing and characterization of memory cells to identify the actual minimum operating voltage for each cell, replacing the need for conservative guard bands. By pre-identifying weakest cells and establishing their specific voltage requirements, the system can operate at lower voltages without sacrificing reliability.
Solution Approach 2:
The patent changes the voltage parameter from a fixed conservative value to cell-specific optimized values. Instead of applying a uniform guard band to all cells, the system determines individual minimum operating voltages through testing and assigns operating voltages accordingly, reducing the overall voltage headroom while maintaining reliability.
Data Source
AI summary
A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.