Horizontal Channel Transistor Isolation via Dielectric Cavity Formation
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Solution Overview
Problem
Existing semiconductor fabrication methods for horizontal channel transistors, such as NWFET and NSHFET devices, face challenges in providing effective electrical insulation to mitigate charge carrier leakage into the underlying semiconductor substrate, particularly in forksheet device designs where tight n-to-p spacing is required.
Innovation Solution
A method is developed to form a semiconductor device by replacing the bottom sacrificial layer with a dielectric layer, using a sacrificial spacer to mask the end surfaces of the upper sacrificial and channel layers during etching, and forming inner spacers to create a cavity for dielectric deposition, thereby ensuring electrical insulation and facilitating the formation of high-quality channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bottom sacrificial layer is used in the device layer stack, then the fabrication process is simplified and channel layers of higher material quality can be formed, but electrical insulation underneath the device is insufficient leading to charge carrier leakage into the substrate
Solution Approach 1:
The device layer stack is segmented into multiple functional layers: a bottom sacrificial layer for cavity formation, an intermediate dielectric layer for electrical insulation, and upper sacrificial layers for channel layer formation. This segmentation allows each layer to perform its specific function effectively, resolving the contradiction between simplified fabrication and adequate electrical insulation.
Solution Approach 2:
An intermediate dielectric layer is introduced as a mediator between the bottom sacrificial layer and the upper sacrificial layers/channel layers. This intermediate layer provides the necessary electrical insulation to prevent charge carrier leakage into the substrate, while the sacrificial layers are selectively removed to form cavities, maintaining both insulation and fabrication simplicity.
2Ease of manufacture
If selective etching is used to remove the bottom sacrificial layer, then a cavity can be formed for dielectric deposition, but the process complexity increases due to multiple etching steps and mask requirements
Solution Approach 1:
The bottom sacrificial layer is formed and positioned in advance before the upper sacrificial layers and channel layers are deposited. This preliminary action allows the bottom sacrificial layer to serve as a pre-prepared template for cavity formation, simplifying the overall process by eliminating the need for complex selective etching sequences and multiple masks.
Solution Approach 2:
The bottom sacrificial layer is designed to be selectively removable by itself through its material properties, serving as a self-contained etch stop and cavity definition layer. This self-service capability reduces process complexity by eliminating the need for additional etch stop layers or complex mask patterns, as the bottom sacrificial layer inherently defines the cavity boundaries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables improved electrical insulation and higher material quality of channel layers by allowing for a simpler device layer stack composition and selective etching processes, enhancing the fabrication of horizontal channel transistors like NWFET and NSHFET devices, including forksheet designs.
Implementation Method 1
further etching the device layer stack to remove the bottom sacrificial layer and thereby form a cavity in the device layer stack
Implementation Method 2
forming a dielectric layer in the cavity, wherein forming the dielectric layer comprises depositing and then etching back a dielectric bottom material
Implementation Method 3
while the sacrificial spacer masks the end surfaces of the upper sacrificial and channel layers, further etching the device layer stack
Implementation Method 4
forming source and drain regions by epitaxially growing semiconductor material on the end surfaces of the channel layers
Data Source
AI summary
A method is provided for forming a semiconductor device. The method includes: forming a device layer stack on a substrate, the device layer stack comprising a bottom sacrificial layer and an alternating sequence of upper sacrificial layers and channel layers; forming a sacrificial gate structure; etching through at least the upper sacrificial and channel layers of the device layer stack while using the sacrificial gate structure as an etch mask; forming a sacrificial spacer covering end surfaces of the upper sacrificial and channel layers; while the sacrificial spacer masks the end surfaces of the upper sacrificial and channel layers, further etching the device layer stack to remove the bottom sacrificial layer and thereby form a cavity in the device layer stack; forming a dielectric layer in the cavity, wherein forming the dielectric layer comprises depositing and then etching back a dielectric bottom material to a level below a bottom-most one of the channel layers; removing the sacrificial spacer; forming recesses and forming inner spacers in the recesses; and forming source and drain regions by epitaxially growing semiconductor material on the end surfaces of the channel layers.