Char Spacer Reduces Load Capacitance in Integrated Circuit Devices
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Solution Overview
Problem
In highly down-scaled semiconductor devices, the increased load capacitance between adjacent conductive patterns due to reduced distances between wiring lines and contact plugs adversely affects operating speed and refresh characteristics.
Innovation Solution
An integrated circuit device structure featuring a conductive line with an insulating capping pattern and a spacer configuration, including an inner spacer and a char spacer with low permittivity, is implemented to minimize load capacitance. The method involves forming a conductive line structure on a substrate, covering it with an insulating capping pattern, and creating a polymer brush pattern that is pyrolyzed to form a char spacer with low permittivity, which is then enclosed by inner and first insulating spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between wiring lines and contact plugs is decreased to achieve high integration density, then the integration density is improved, but the load capacitance between adjacent conductive patterns increases
Solution Approach 1:
The patent applies local quality by creating a spacer structure with non-uniform thickness - a first spacer portion with greater thickness adjacent to the conductive pattern and a second spacer portion with lesser thickness farther away. This localized variation in spacer thickness provides enhanced capacitance reduction exactly where needed (near the conductive pattern) while maintaining overall integration density benefits.
Solution Approach 2:
The patent employs composite materials by combining the spacer material with different dielectric properties in different regions. The spacer structure uses material composition variations to achieve optimal electrical isolation - utilizing materials with appropriate permittivity characteristics to minimize capacitive coupling between adjacent conductive patterns while maintaining physical integrity.
2Productivity
If the distance between wiring lines and contact plugs is decreased to achieve high integration density, then the integration density is improved, but the operating speed is adversely affected
Solution Approach 1:
The locally varied spacer thickness concentrates the capacitance-reducing effect in the critical region near the conductive pattern, thereby improving signal transmission speed where it matters most for device operation, while allowing other regions to maintain compact dimensions for high integration density.
Solution Approach 2:
The patent changes the geometric parameter of the spacer (thickness) as a function of position, creating a gradient structure that optimizes the balance between capacitance reduction for speed and dimensional constraints for density. This parameter variation enables simultaneous improvement of both operating speed and integration density.
3Productivity
If the distance between wiring lines and contact plugs is decreased to achieve high integration density, then the integration density is improved, but the refresh characteristics are adversely affected
Solution Approach 1:
By concentrating the spacer thickness increase adjacent to the conductive pattern, the invention provides localized electrical isolation that specifically addresses capacitive coupling affecting refresh operations, while maintaining overall device compactness for high integration density.
Solution Approach 2:
The use of spacer materials with optimized dielectric properties creates a composite structure that reduces parasitic capacitance, thereby improving charge retention and refresh characteristics in highly integrated devices where conductive patterns are closely spaced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces load capacitance between conductive patterns, enhancing the operating speed and refresh characteristics of miniaturized cells with high integration density by utilizing a char spacer with low permittivity.
Implementation Method 1
A char spacer is formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen
Data Source
AI summary
Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.