Charge-Domain CIM Circuit With Passive Summation for Low-Power Accuracy
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Solution Overview
Problem
Conventional compute-in-memory (CIM) designs for convolutional neural networks (CNNs) face challenges in achieving low power consumption and high accuracy, with existing solutions being neither power-efficient nor high-accuracy.
Innovation Solution
A CIM circuit with charge-domain passive summation using a first processing circuit that includes a first data-selection circuit and a first charge-domain passive summation circuit, utilizing a weighted capacitor array integrated with a memory array to generate analog computation results through charge redistribution, and employing calibration techniques to address inter-buffer mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional CPU or bit-wise current-based CIM circuits are used for convolution operations, then the system can perform AI computations, but power consumption is high and accuracy is limited
Solution Approach 1:
The patent replaces conventional digital computation mechanisms (CPU or bit-wise current-based CIM) with an analog charge-domain computation mechanism. The weighted capacitor array performs multiply-accumulate operations through charge redistribution, where the charge on each capacitor represents the weighted sum result. This analog approach eliminates the need for high-speed digital switching and reduces power consumption while maintaining computation accuracy through precise charge storage.
Solution Approach 2:
The patent changes the domain of computation from digital (voltage or current levels representing binary bits) to analog charge domain (where charge magnitude directly represents weight values). By storing weights as charge values on capacitors and performing computations through charge redistribution, the system achieves both low power consumption and high accuracy. The calibration circuit further adjusts charge parameters to compensate for manufacturing variations, ensuring computation precision.
2Adaptability or versatility
If separate weight storage and computation circuits are used, then the system can perform flexible computations, but device complexity and area increase
Solution Approach 1:
The patent merges the weight storage function and computation function into a single integrated structure. The weighted capacitor array serves dual purposes: it stores the weights (as charge values) and simultaneously performs the multiplication and accumulation operations. The selection circuit integrates weight selection with the computation process, allowing flexible weight configuration without requiring separate storage and computation blocks. This integration dramatically reduces circuit complexity and area while maintaining computational versatility.
Solution Approach 2:
The weighted capacitor array is designed as a universal computation resource that can perform multiple functions. The same capacitor array can store different weight sets by reconfiguring the selection circuit, enabling the system to adapt to different neural network layers and operations. The calibration circuit provides universal compensation for various sources of error, making the computation engine versatile across different AI workloads without requiring dedicated hardware for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves reduced power dissipation and high accuracy in CIM operations by integrating a weighted capacitor array with the memory array, enabling direct multi-bit operations and reducing parasitic capacitance, while also correcting inter-buffer mismatches to maintain classification accuracy.
Implementation Method 1
performing, by a weighted capacitor array integrated with the memory array, charge-domain passive summation to generate an analog computation result of an input and the target weight
Data Source
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AI summary
A compute-in-memory (CIM) circuit includes a processing circuit. The processing circuit includes a data-selection circuit and a charge-domain passive summation circuit. The data-selection circuit includes a memory array and a selection circuit. The memory array stores a plurality of candidate weights. The selection circuit selects a target weight from the plurality of candidate weights stored in the memory array. The charge-domain passive summation circuit generates an analog computation result of an input received by the processing circuit and the target weight stored in the memory array through a weighted capacitor array integrated with the memory array.