Charge-Domain Filter Clock Tuning for Gain and DC Offset Control
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Solution Overview
Problem
Charge-domain filters (CDFs) face gain variation and DC offset issues due to process variations, which affect the performance of variable gain amplifiers in analog-to-digital converters, and the sampling pulse width is inversely proportional to the input sampling rate, leading to gain variations or losses depending on the filter bandwidth.
Innovation Solution
A charge-domain filter with a switched-capacitor network and a clock generator that adjusts phase differences and pulse widths of clock signals using unit pulse cells and programmable width cells to compensate for process variations, maintaining constant gain and stable DC levels across different bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sampling pulse width is decreased to increase the input sampling rate, then the productivity is improved, but the gain variation increases
Solution Approach 1:
The patent changes the pulse width parameter of clock signals dynamically to compensate for gain variation. When the sampling rate increases and pulse width decreases, the system adjusts the switched-capacitor network parameters to maintain constant gain, directly applying parameter changes to resolve the contradiction between productivity and manufacturing precision.
2Adaptability or versatility
If the CDF performs charge samplings to improve signal processing, then the functionality is improved, but the DC offset increases
Solution Approach 1:
The patent implements a feedback mechanism where the system monitors the DC offset generated during charge sampling and adjusts the clock signal parameters accordingly. The feedback loop modifies the pulse width or phase to compensate for DC offset, allowing the CDF to maintain signal processing capability while reducing harmful DC offset effects.
3Productivity
If the bandwidth is increased to improve filtering performance, then the productivity is improved, but the gain loss increases
Solution Approach 1:
The patent applies dynamics by making the clock signal pulse width adjustable and adaptive. As bandwidth increases for better filtering performance, the system dynamically adjusts the pulse width parameter to compensate for gain loss, transforming a static system into a dynamic one that adapts to different operating conditions to maintain constant gain.
Data Source
AI summary
A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.