Charge Fixing Layer Reduces Effective Channel Thickness
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Solution Overview
Problem
Semiconductor devices with traditional planar transistor structures face challenges in achieving high integration and efficient channel characteristics, particularly in reducing the effective thickness of the channel layer to prevent disconnection defects while maintaining physical thickness for reliability.
Innovation Solution
A semiconductor device with a vertical structure incorporating a charge fixing layer made of high-k material or metal, which accumulates negative charges to reduce the effective thickness of the channel layer, thereby improving threshold voltage and current characteristics, and is physically separated from the conductive pad to prevent material deposition interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical thickness of the channel layer is reduced to improve integration, then device integration increases, but reliability deteriorates due to disconnection defects
Solution Approach 1:
The patent introduces a vertical transistor structure with a charge fixing layer positioned at a different vertical dimension within the channel layer. This allows the effective channel thickness to be reduced for better integration while the physical channel layer maintains sufficient thickness for reliability. The charge fixing layer creates an electric field that modulates the effective channel thickness without requiring physical thinning of the entire channel layer.
Solution Approach 2:
The charge fixing layer is positioned specifically within the channel layer to locally modify the electric field distribution. This creates a localized reduction in effective channel thickness where needed for integration, while other regions of the channel layer maintain their physical thickness for reliability. The high-k or metal material of the charge fixing layer provides localized charge accumulation to achieve this differential effect.
2Manufacturing precision
If a charge fixing layer is introduced to reduce effective channel thickness, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The charge fixing layer is merged with the channel layer formation process, using the same high-k or metal materials that are already part of the vertical transistor stack. This integration approach allows the charge fixing functionality to be added without requiring entirely separate processing steps, thereby limiting the increase in device complexity while achieving improved electrical characteristics.
3Reliability
If the charge fixing layer is placed close to the conductive pad for connectivity, then electrical connection is improved, but material deposition interference occurs
Solution Approach 1:
The patent positions the charge fixing layer as an intermediary element between the channel layer and the conductive pad, but maintains a deliberate physical separation. This intermediary positioning allows the charge fixing layer to fulfill its electrical function while preventing direct contact that would cause material deposition interference. The separation distance is optimized to maintain electrical functionality while avoiding manufacturing issues during material deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The charge fixing layer effectively reduces the channel layer's effective thickness, enhancing electrical characteristics such as threshold voltage and current performance while minimizing the risk of disconnection defects, even when the physical thickness is maintained for reliability.
Implementation Method 1
a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal... The charge fixing layer may be configured to reduce an effective width of the channel layer during an operation of the semiconductor device to less than a physical width of the channel layer by accumulating negative charges
Data Source
AI summary
A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.